What is annotation, SDF

[mouzid]

what is the sdf

Hello,
To design a circuit I know that we have to do Schematic capture, Simulation, the Layout drawing the DRC. Anf inaly extraction and LVS.
I heared about a new things: annotation and SDF.
Could someone explain what is annotation and SDF ?
Where this task is done in a design flow. What tool are used for that and
How to do it ?

 

[dmk]

how to claculate delays in *,sdf file

Annotation means to put reference designator of the circuit. InOrCAD Capture you do it with Tools/Annotation.
SDF means Standart Delay File and is used in Verilov and VHDL design to include timing when simulating the circuit.

 

[deva_eda]

what is annotating

SDF = Standard Delay Format.

Typically in design flow you flow from architecture, RTL, simulation, synthesis, floor planning, layout design .. just as you mention.

To explain where SDF is generated and whats is use. Let me tk the case of synthesis. As you know after synthesis you get the gate level netlist. Which is nothing but the functional description of you logic in gate level.

But what about the typical, gate delays an wire delays that you have at silicon level. This is not embeded in the netlist. But it is stored differently in different file called "Standard delay format (SDF)". That contains the delays. So typcillay when you do gate level simulation your requrie even SDF to simulate as closely as the simulation in the physical device i.e with delays.

The point is where all do we annotate this SDF, the point is linked with the how accurate is the delay value in the SDF. The dealy values in the SDF are close to real physical delays aftef PnR and layout is done. The SDF extarcted here has more accurate delays.

 

[skyfaye]

annotation in sdf

Back annotation of the SDF file means you're configuring the delays, setup/hold checks, etc. back to your netlist. There are several steps in the back-end process that can generate an SDF file but the most timing accurate one is after routing and is usually the one used in gate-level simulation with timing (i.e. back-annotating the SDF). All the functional simulation tools support back-annotating SDF files and is very simple to do.

 

[dmk]

Yes, it was my mistake -> SDF = Standard Delay Format file.

 

[tariq786]

annotation can be forward and backward. Forward annotation for calculating delay means you provide hints to the timing analyzer e.g Prime Time information about the layout of your design without actually doing the layout so that it can better estimate delay.

Backward annotation means after doing the actual layout, you pass the information back to the timing analyzer to calculate the new more realistic delay.

For more information, see the book

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime by
Himanshu Bhatnagar