Are you already familiar with how PT will "expand" the periods of two clocks with different periods in order to find e.g. the least-common-multiple time where both clocks have a coincident edge?
(e.g. the effective period gets expended in the timing-report in order to find the tightest slack path between the two clocks)
I suspect (even though nothing shows up in SolvNet) that "unexpandable" means that PT could not eventually find an interval where "beating" of the two clocks occurs in a repeating pattern.
The assumption here is that PT gives up after iterating over larger and larger multiples of the period to find a common repeating pattern.
The bottom line is that you are either mis-defining your clock periods, or else you are overlooking e.g. false-path or set_max_delay declarations between totally unrelated clocks.
BTW, coincidentally there is an article that talks about this exact topic which you should read.
It is in the latest Xilinx Xcell Journal # 85, available on Xilinx's website, starting on page 30: "Demystifying Unexpanded Clocks".
While this is talking about Xilinx's Vivado timing analyzer, I feel the content is applicable to PT as well (noting Vivado supports the Synopsys SDC format for timing setups).