What is a loop on a PCB?

szza009

Hi,

We have an application and it pass all EMC tests(surge, eft etc..) except RF Immunity 80Mhz-2Ghz and 30V/m. You can see a part of our pcb below. Do you think it has a loop? It fails at frequency range 300Mhz-550Mhz. What is the exact mean of a loop for a PCB?

10x.

pcb design loops

is it 2 layers?
if more, then how far is the nearest GND plane for the signal layers? I think it should be small.

If there is no continous GND under all traces, then there are loops.

pcb return loop

ALL signals on ALL PCB's are loops. There is the signal path that you see as an individual trace that you or the autorouter placed on the board - that is only one side of the signal path. The other side of the signal path, the return side, runs through the ground or power planes or traces. Conservation of energy drives this unseen signal return to run as close as physically possible to the signal trace.

If you have been careless laying out your board, you force the return path away from the signal trace creating a larger "loop" than necessary. It is these exaggerated loops that generally cause the problems with a board.

When laying out a PCB it is ESSENTIAL that the entire signal path be kept in mind. You MUST provide an adequate return path as near as possible to the signal trace. Usually, this is done by including an adjacent, continuous, plane under every signal trace.

buenos said:

is it 2 layers?
if more, then how far is the nearest GND plane for the signal layers? I think it should be small.

If there is no continous GND under all traces, then there are loops.

Click to expand...

Hi,

Yes, it is two layers. Bottom layer is mostly grounded. Top layer is for signal routing. But it is still influenced by RF 300Mhz-550Mhz.

House_Cat said:

If you have been careless laying out your board, you force the return path away from the signal trace creating a larger "loop" than necessary. It is these exaggerated loops that generally cause the problems with a board.

When laying out a PCB it is ESSENTIAL that the entire signal path be kept in mind. You MUST provide an adequate return path as near as possible to the signal trace. Usually, this is done by including an adjacent, continuous, plane under every signal trace.

Click to expand...

Is there any program to analyze PCB for larger loops than necessary?
I'm using Orcad layout and routing manually.
10x.

Hi, two-layers board is hard to simulate, becuase it is impossible to fix the ways of the current flow. You should try to use Hyper 7.7, it seems that it is possible to simmulate two-layers boards with it

try to read this articles

PCB Design Guidelines For Reduced EMI
h**p://focus.ti.com/lit/an/szza009/szza009.pdf

Partitioning and Layout of a Mixed-Signal PCB
h**p://www.hottconsultants.com/pdf_files/june2001pcd_mixedsignal.pdf

Best regards!
avesat

Do you have vias connecting the top and bottom grounds? I can't see any.

maybe you should consider using 4 layers. more expensive. although theoretically possible to make your board work on 2 layers, but on 4 layers there is a much bigger chance.

you should follow all your longer traces, if there the gnd is continous or not. if not, how far does the gnd current have to go away from your trace? -to follow the signal trace.

BasePointer said:

Is there any program to analyze PCB for larger loops than necessary?
I'm using Orcad layout and routing manually.
10x.

Click to expand...

There's no software that will automatically tell you what the loop size may be. There are just too many variables to take into account. The best advice is for you to look at the layout and see what the nearest return path could be. Your eyes will tell you how far the return current is going to have to go to get from the source to the sink on your board. You should also be able to see where there are going to be multiple signals forced to share a portion of the return path (another source of noise and signal quality loss).

Buenos is right, you would be better off with at least a four layer board.

difflvl said:

Do you have vias connecting the top and bottom grounds? I can't see any.

Click to expand...

Hi, yes we have a lot of vias connecting the top and bottom grounds. Gif file doesn't show them. I don't know why but actually there are a lot.

Added after 3 minutes:

House_Cat said:

Your eyes will tell you how far the return current is going to have to go to get from the source to the sink on your board.

Click to expand...

My braing is going down after a few hours later while looking the pcb and I start seeing everythink as if there was lines.

Added after 3 minutes:

avesat said:

Hi, two-layers board is hard to simulate, becuase it is impossible to fix the ways of the current flow. You should try to use Hyper 7.7, it seems that it is possible to simmulate two-layers boards with it

try to read this articles

PCB Design Guidelines For Reduced EMI
h**p://focus.ti.com/lit/an/szza009/szza009.pdf

Partitioning and Layout of a Mixed-Signal PCB
h**p://www.hottconsultants.com/pdf_files/june2001pcd_mixedsignal.pdf

Best regards!
avesat

Click to expand...

Thank you for the links. I have downloaded Hyperlynx 7.7 but I couldn't install it. Do you have any installation instruction for it?
I also wonder that I'm using orcad layout plus for the pcb and can I analyze it with hyperlynx?

10x

Added after 1 minutes:

buenos said:

maybe you should consider using 4 layers. more expensive.

Click to expand...

Unfortunately, we can't use four layers due to cost

BasePointer said:

buenos said:

maybe you should consider using 4 layers. more expensive.

Click to expand...

Unfortunately, we can't use four layers due to cost

Click to expand...

I know this is hard to sell to management, but sometimes that cost savings on a 2-layer board ends up costing you more in the long run with signal integrity issues. In the past I have seen 2-layer designs that have worked great until a supplier makes a change to their chip (like a die shrink) and now that part is running faster and those signal integrity issues that you are sure you never had all of a sudden start popping up. Even worse is when problems are found by a customer and it causes them a line down situation.

BasePointer,
if you want to use Hyper 7.7 you need at least one ground plane, for simulation, please read the helps in Hyper.

If your circuit fails with a external frequency, you can check, some step.

The board grounding probably are not enough. You can try EMI filters o bypass in specific signals, properly.

Skywalker.

skywalker said:

BasePointer,
if you want to use Hyper 7.7 you need at least one ground plane, for simulation, please read the helps in Hyper.

If your circuit fails with a external frequency, you can check, some step.

The board grounding probably are not enough. You can try EMI filters o bypass in specific signals, properly.

Skywalker.

Click to expand...

There is the extract from the HL 7.7 documentary:

Assume Distant Ground When No Plane Layers Exist
If you use double-sided or flexible boards with no plane layers, you no longer must create a “fake” reference-plane layer in the stackup to enable simulation. The field solver now assumes that a distant plane layer exists, if no plane layers exist in the stackup.

Assume Distant Ground if No Plane Layer Exists
When this option is enabled and no plane layers exist in the stackup, the field solver assumes that a distant plane layer exists during its calculations. The field solver knows just how far away from the signal layers to put the “hidden” plane to get the right answers with good speed and accuracy. If you use double-sided or flexible boards with no plane layers, enabling this option means that you do not have to manually create a “fake” plane layer in the stackup to enable simulation.

Hi to all,

We connected some ground planes to each other and the problem was absolutely solved.

10x