What is a DDR register in FPGA?

[richardyue]

Hi, Members,
What is DDR register? I want to know its role in FPGA and the basic structure of it. Thanks in advance.

 

[echo47]

xilinx ddr register

That's a Double Data Rate register. It has two clock inputs, and behaves like a very fast two-bit parallel-to-serial or serial-to-parallel shift register. Twice as fast as a regular register. One common way to clock a DDR register is to feed it your regular CLOCK and inverted-CLOCK.

In many FPGAs, DDR registers are available only at the input/output pins, but they are still very useful for communicating with a fast external device such as a DDR SDRAM.

Here are descriptions of Xilinx input and output DDR register primitives (named IFDDRCPE and OFDDRCPE) available in some FPGAs:
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The DDR register details vary between different FPGA types, so read your specific FPGA data sheet.

 

[richardyue]

shift register ddr

Hi, echo47
I want to ask you a private question. Would you like to tell me what your job is. You have helped me a lot. I think you must be an expert in the PLD field. But, you know, I'm a really newbie in this field. I want to change my job into the ASIC/FPGA. I've read lots of books, but it's not so easy without any practice. I'm kind of losing myself.