What is a "datapath compiler"?

[boardlanguage]

I have used Design Compiler and Cadence Ambit/PKS5 to synthesize RTL-code with a lot of arithmetic (+, -, *.) This generates a gate-netlist for my (standard-cell) technology-library (Artisan TSMC.)

Now, someone told me that designs which use lots of arithmetic can get better timing/area, if I use a 'datapath compiler'? What is that? Is that an optimized RTL -> standard-cell ASIC synthesis tool? Or is it some kind of automated semi-custom cell generator?

What's the usage-flow for a datapath-compiler? Do I need to use a special ASIC library with the datapath-compiler? Do I just give it my unmodified VHDL/Verilog RTL? Or do I need to modify/convert my RTL into a special format?

 

[edaguy69]

It depends on the nature of your design which determine what kind of compiler you should use

 

[boardlanguage]

So have you used a datapath compiler before? How does it give you synthesizeable-RTL? Or does it work at a physical level, giving you a custom layout?

 

[laglead]

data path does not contain storage element. So data path complier deal with combination logic.

 

[littleyard]

As I konw that, the "Datapath Compiler" is generally used to sythesis those design target for high speed and with a lot of arithmetic calculations. Just like the CPU datapath. I do not think it need special library to support, but need special license for your Design Compiler. Why not check with you Synopsys FAE for this? He will give you a detail support on this!

 

[boardlanguage]

Thanks guys.

I was under the impression that the arithmetic units in a datapath heavy design were synthesized using a special method. For example, the math-units on a lot of ASICs aren't standard-cell -- if you look at the die-photograph, you can see where the ALU-unit is separated from the rest of the standard-cell logic.

Anyway, I know companies like NVidia and ATI (now AMD) used dataptah-synthesis to achieve very high clock-speed and/or logic-density on the math-functions in their designs. But I wasn't sure if they just went to a third-party EDA tool solution, push a button, and then get a special RTL-output (or placed-netlist), or if they had an inhouse backend-team manually re-do a semi-custom layout for the identified math-units.

A former contractor at NVidia said it was the latter, with some critical arithmetic logic units getting special-treatment (semi-custom layout to replace the original RTL.) Both the non-critical math units were synthesized normallly, using a conventional RTL-synthesis tool (like DC-Ultra.)