What is a concept of ZERO DELAY BUFFER ??

[jay_ec_engg]

Hi ..
what is the concept of zero delay buffer ?
for what purpose it is used and what is the logic ?

 

[papyaki]

Hi,

For such buffer, signal transition from input to output is equal to 0. It is mainly used for high speed clock distribution on a board.
Clock source is connected to several buffer inputs and is distributed to different branches.
By having 0 delay between inputs and outputs, raising and falling edge of the clock occurs in the same time, on each branch of the distribution.

 

[cube007]

Hello,

Because the reality does not allow a zero delay these buffers are using a PLL (phase lock(ed) loop) to achieve a “zero” delay.

Bye,
cube007

 

[jay_ec_engg]

Zero delay in the sense... upto what freq it will work .. i mean what is the dealy time ?? its in nano sec or pico sec ??
is this a tech or some ICs are used for the same ..

 

[cube007]

More information is available from IDT (https://www.idt.com/products/clock_management.html). IDT is developing a lot of devices for clock management. For specification about Zero Clock Buffers take a look at here: **broken link removed**


Bye,
cube007

 

[chinara]

You also should note that one of pins is a feedback pin to control the clock screw. the pin should have same load with other pins. The phrase of the output clock may be adjust by this way.