A buffer is a courrant amplifier. It is used when you need to drive a lot of gate with the same signal. Tipicaly a clock is distributed to all cells inside a fpga. So the clock signal is buffered before going to all cells.
I took "courrant amplifier" as "current amplifier". Did I make it right?
I learned a pair of inverters could be used as a buffer when I read Synopsys books.
Can anyone tell me where to look for more info about the structure, attribution of the buffer, like the Synopsys reference or datasheet of a standard cell library?
Synopsis make access to the library of the Silicon Foundry or the FPGA
industry you are working with. So the term "buffer" is related to those libraries.
Is this something related with replication, when a net is split, driven by multiple buffers, each buffer will drive a low amount of destinations, reducing the net loading ?
You are correct. One important use of buffers is to split the clock lines into several portions and drive them separately so that the rise and fall times are not degraded by the buffer limitations of current pull up and pull down. Special care is to be taken to make sure all of the buffers are identical so that propigation delay is equal between them. This is no problem on a single IC. In the case of a design using commercial ICs it is important that all of the buffers are on the same IC so that they are more likely to be identical. In some logic families, like ECL, there are special ICs that have many buffers all connected to the same input. They are frequently called "clock driver" like the Motorola MC100E111.
Synthesis tools will insert the clock buffer by means of loading balance, clock tree branch, place and route. Not just insert some buffer in the middle of clock path.
Buffers have "buf" footprint property.
Normally buffers are inserted to solve timing and drc (including fanout,slew/transition time...) problems.
CTS-buffers are inserted to balance clock sink pins, both rising and falling edge should be taken into account.
see buffer in layout, it is really two inverters. the size of buffer is just the W/L of your process which may vary in drive ability. we use buffer to do CTS, to fix high fanout net , to fix long wire etc...
Obviously asicer means the second case. Buffer=driver, which actually is two cascaded inverted.
Design tools choose from the library the buffer component with the apropriate drive strength taking into account fanout, timing contraints etc.
In a general sense it can be said that buffer is an element that replicates its input at its output.
You use a buffer for two reasons one for fanout of a digital circuit; the other is adjusting the delay between different signal paths.
Lets consider the first case: suppose that you have a signal output and u can drive with this output only two input. Lets say you want to drive four outputs. Now what will you do ?? Here u use two buffers. Your signal can drive this two buffers succesfully. The buffers replicate their inputs at their outputs and u apply the 4 outputs of your buffers to 4 inputs that u requested to drive.
Lets consider the second one: suppose that you have two signal paths that are drived by a clock but because of layout considerations one of your signal paths must be more lengthy; But you want the clock to reach at the same time two their targets How can you fulfill this condition ?? Of course by delaying the faster signal on its path. Buffer is a nice delay element because of its input capacitance. You put this on your faster signal path and you fulfill the condition.
In simulation tools a buffer resambled by two inverter. If you cascade two inverter it replicates its input at its output. That's why two inverter can resamble a buffer.