what if skew required not matched?

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veenanjaliallada

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if the timing and performance are ok for the chip but skew reqired did not meet can the chip be taped out?
 

What do you mean by "skew reqired did not meet" ?
 

every design has certain target skew to be met.
Whats the issue faced if we exceed that skew targets but still meet our timing requirement

- - - updated - - -

i mean if our timing,congestion,performance are ok but we have worst skew can we proceed to tape out?
 
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I am not aware of that requirement. We usually have timing/area/power requirements on a design. But skew?? Usually any skew can be tolerated if the functionality is not affected.
 

veenanjaliallada said:
if the timing and performance are ok for the chip but skew reqired did not meet can the chip be taped out?
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When you can MET the timing and achieve other requirement, this means your clock skew is not problems.
Because if your skew is so bad, you can'e met the timing.
 

Skew limits are imposed on the design due to statistical variation in the clock tree on chip. If the difference is too much .... it is better to keep the skew variation to the minimum so that the variation tracks across Process voltage and temperature and silicon variations.
 
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