In this case , when FPGA is overloaded....means your code design will not fit into the device which u have selected...........
you have chosen such a device which is not large enough to implement the hardware your code is going to generate. You will need to either try to optimize your code, your layout, or move to a larger device. .............
or chose another device which hav e much larger capacity then this device......
If FPGA is overloaded ,then u canot do the Place n Route ,Mapping ,that to u cannot generate .bit map file..............
only u can check the hardware...........
the code is not get doen loaded........