what happens to the timing statements during synthesis

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FixitFast

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hi all

my question is based on following code snippet that I have seen on the 3rd party development kit I am using


Code: 
...
...
case reset_state_r is
...
... 
when RESET_DISABLE_CLK =>
                  en_clk_off_cnt_r <= (en_clk_off_cnt_r + '1') after (100)*1 ps;
                  if (TO_INTEGER(unsigned(en_clk_off_cnt_r)) = (EN_CLK_OFF_CNT - 1)) then
                     reset_state_r <= RESET_DEASSERT_RST after (100)*1 ps;
                  end if;
...
...

so what will synthesize of the following statement in the above snippet
Code: 
en_clk_off_cnt_r <= (en_clk_off_cnt_r + '1') after (100)*1 ps;
What I want to know is the timing.
 

The timing is all stripped off - it is meaningless in an FPGA. Timing statements are for simulation only.

These statements may have been put in to model the behavior of a specific device, and when you change devices, they are probably now incorrect. Or they may just be useless in the first place.
 

Thanks for reply.

so you mean to say that after stipping of the timings (i.e. non-synthesizable part) the rest of the thing will be transformed into form of gates or will they be ignored completely.
I mean it is not like using,
synthesis on - synthesis off statement, right!

I emphasis more on this because the part I am talking about is usthe module for clock and reset distribution. It is using virtex-6 powered board.

and
Code: 
            -- Default assignments
            en_clk_capture  <= '0' after (100)*1 ps;
            rst_rsync_pre_r     <= '1' after (100)*1 ps;

will only be read as following by synthesizer?

Code: 
            -- Default assignments
            en_clk_capture  <= '0' ;
            rst_rsync_pre_r     <= '1' ;

bests
fixitfast
 
Last edited:

Think of it as ... only that which is recognizable as something synthesizable will be synthesized to hardware (gates). Everything else is gleefully ignored.

- - - Updated - - -

So that "after 100 ps" stuff might mean something for simulation, but means nothing for synthesis (and will be ignored).
 

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