What happens to hardware if there is no else condition in always block?

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mm_pk1

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Following is a small piece of code. I wanted to know that if there is no else condition in connection with previous if condition, what kind of hardware will be made after synthesis.

Code: 
output [3:0] OUT;
input [3:0] BusIn;
reg [3:0] data;
assign OUT = data; 
always @ (posedge CLK)
   begin
      if(~Flag)
            data <= BusIn;
     else  
            date <= data; //what will be the hardware if i omit this line of code
   end
 

hello,

If you mean to ask that if there will be any unwanted Latch developed or not, then since this is synchronous ckt, hence if you do not add any thing your data will retain there.
Since it is a FF developed change changes state on next Clock state and no else means no activation for the FF in next clock cycle.
 

In a synchronous bit of clode (like yours) then the if/else tree will be connected to the clock enable port of a register. So you can omit the else branch (in theory, it could build you a mux connected to the D input instead of a clock enable connection, which you probably wouldnt want, but it's usually good enough to connect to clock enable instead.).
 

So you can omit the else branch (in theory, it could build you a mux connected to the D input instead of a clock enable connection, which you probably wouldnt want, but it's usually good enough to connect to clock enable instead.).
Click to expand...
As the "else data <= data" alternative is logically redundant in synthesis of clock synchronous registers, you can expect that the gate level logic looks the same. A multiplexer might be used though - if the respective FPGA family doesn't have clock enables with their registers.
 

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