What happens if timescales are different in different files of the same design?

[gold_kiss]

What happens if `timescale are different in different files of the same design? I mean say our design has 4 files inall. And in 2 of them I specify `timesacle 1ns/1ps
and for the remaining 2 files i specify `timescale as value as `timescale 100ns/10ps


Does my design end up giving wrong results? Or will I get errors during simulations?

Cheers,
Gold_kiss

 

[Laplace]

verilog timescale

why don't you try and see?

Active HDL's earlier versions were employing lowest precision for the entire design....

 

[z81203]

change the time scale in verilog

i remember you would got a warning. it's depend you top level file(maybe stimuli file).

 

[yusq]

include timescale verilog

I think no problem if all of the files (including the libraries) has timescale. However, if the verilog library( with time infor) does not contain timescale information, the order of the files may have effect on the simulation results. however, the larger the defference between the time unit and the time pricision, the more time the simulator will take to run the simulation.

 

[eexuke]

verilog changing the timescale

The simulator will raise up a warning under this situation,but it doesn't matter.
Normally,the time scale in RTL design is not very critical or accurate.You'd better pay more time to your pre-layout & post-layout simulation.That's make sense.

 

[pahol]

what is verilog timescale command

I think the best way, you should get the evaluation of simulator and test it.

 

[crystal]

verilog override timescale

In Verilog, compiler directives, like `timescale, apply across file boundaries. The directive is in effect until it's overridden by a subsequent `timescale compiler directive.

For example, consider the following 3 files:

a.v
====
`timescale 1ns/1ns
module A;
...
endmodule

b.v
===
`timescale 1ps/1ps
module B;
...
endmodule

c.v
===
module C;
...
endmodule

So, if you compile these files in the order
a.v b.v c.v
then module C will have a timescale of 1ps/1ps, the same timescale as module B which appears before it in the file order on the command line.

If you compile these files in the order
a.v c.v b.v
then module C will have a timescale of 1ns/1ns, the same timescale as module A which appears before it in the file order on the command line.

To avoid this file order dependancy and the problems that could result from it, it's highly recommended to include a timescale directive in every Verilog source file.

 

[g3nster]

nc verilog +nc override timescale

I think it all depends on the Top level module and belivev that the simulator will complain

 

[farmerwang]

ncveriolg override timescale

Simulator will not change the `timescale until it encounter a new one, so the simulation result depends on the order of the file you compiled. If you simulate with NC-Verilog, the first file must have a `timescale directive if any of your files contain a `timescale directive.