What Happens if the variable of the if statement is multi bit?

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pkoti83

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In DUT:-

Code Verilog - [expand]
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module Dut
input a,b;
 
input [1:0] s1;
 
output out
 
always@(s1 or a or b)
begin
 if(s1)
 out = a;
else
out =b;
 
 
In TestBench:
 
module TB;
 
output reg a,b;
 
output reg[1:0] s1;
 
input out;
 
Dut d1(.a(a), .b(b), .s1(s1), .out(out));
 
initial 
begin
#50 s1=2'b10, a=1,b=0;
#50 s1=2'b11, a=1,b=0;
#50 s1=2'b01, a=1,b=0;
#50 s1=2'b00, a=1,b=0;

why the o/p = 1, When i drive s1=2'b10 and what is the reason? On what basis it will be executed?

why the o/p = 1, When i drive s1=2'b11 and what is the reason? On what basis it will be executed?

why the o/p = 1, When i drive s1=2'b01 and what is the reason? On what basis it will be executed?

why the o/p = 0, When i drive s1=2'b00 and what is the reason? On what basis it will be executed?

In another case width of s1 is a 3 bit vector in both DUT and Testbench and apply different stimulus like

#50 s1 =3'b0x1; a=1;b=0;
#50 s1 =3'b1zz; a=1;b=0;
#50 s1 =3'b01z; a=1;b=0;
#50 s1 =3'bzzz; a=1;b=0;
#50 s1 =3'b01x; a=1;b=0;
#50 s1 =3'b1zx; a=1;b=0;

on what basis if-else statement will be executed?
 
Last edited by a moderator:

In simple words, you are asking what if (s1) means for a multibit value s1. You can elaborate it as if (s1 != 0), the expression is true if any bit is not zero, an reductive or operation.
 
If i drive s1 = 2'b0x, 2'bz0, 2'bzz, 2'bxx, 2'b1x and 2'bz1;

Whether the above value of s1 is true or false?

and why? How it will be executed
 

Please read Section 12.4 Conditional if–else statement of the 1800-2012 LRM. And I'll give you a little help by saying that only the last two values 2'b1x and 2'bz1 are known non-zero values.
 

I Need to check the above conditions in VERILOG.

If(s1) where s1 is driven to 2'bx0, 2'bz0, 2'bxx, 2'bzz.

whether the above conditions are synthesizable? If yes, how?

What will be the simulation results in verilog
 

whether the above conditions are synthesizable
Click to expand...
You're on the right track. Neither x nor z are synthesizable as input values. That's why the discussion is almost meaningless for synthesized code. It's mainly a question of possible simulation mismatch.
 
If you start talking about SYSTEMVERILOG, then X and Z can be used as wildcards for input patterns.

But synthesis tools never consider the propagation of X and Z values, they are simulation artifacts. However a simulator may produce values that are different from what the synthesized hardware produces.
 
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