what happens if 2nd interrupt occurs while the ISR of the 1st is being executed

An interrupt causes a microcontroller/microprocessor to leave the normal execution flow and execute an ISR. Interrupts can have priority over other interrupts.

What happens if an interrupt occurs and its interrupt service routine is being executed and before it finishes, another interrupt occurs? Will the processor move to executing this 2nd interrupt once the current service routing reaches its end? How is this usually dealt with as I am sure such a scenario is quite common.

on PIC MCU
GIE bit is OFF when entering inside interrupt treatment
and will be put ON at the end of interrupt
so only interrupts with the correspondig Flag interrupt allready "ON" could be executed inside one interrupt.
so next IT treatment will occur just after return to the main..

it is the main reason to keep interrupt treatment as short as possible
and do each specifique treatment in the main.


but you can have 2 levels of interrupt ...
or more with ehanced MCU (PIC24 PIC32 ) .. with many priority levels.

matrixofdynamism said:

...... Will the processor move to executing this 2nd interrupt once the current service routing reaches its end? How is this usually dealt with as I am sure such a scenario is quite common.

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If an interrupt service routine is in progress , then that can be interrupted by a higher priority interrupt.

OK, if an ISR is in progress and a lower priority interrupt occurs, will it be ignored or will it be carried as soon as the current ISR ends?

It would be strange to ignore any interrupt so normal practice would be to run (or resume) the low priority interrupt as soon as the high priority one finished.

Brian.

It depends on the priority of the interrupt when the interrupt subroutine is performed.

OK, in that case, is it that interrupts will always have priority in every system? I mean, is this always held true?

matrixofdynamism said:

OK, in that case, is it that interrupts will always have priority in every system? I mean, is this always held true?

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yes. priority is always there when there are more than one interrupt request.

That's the reason for assigning interrupts. All the systems carry interrupts within themselves. Priority should be assigned if there is more than one interrupt.

Normally interrupts are not reeabled when the interrupt service routine is run, so it will finish executing, and the pending interrupt with the highest priority will then take control when interrupts is reenabled at return from interrupt.

Note that you have to reeable the interrupt system in the ISR yourself. Before you do that, you need to be very certain that your code is fast enough to serve any interrupt situation, and it has to be reentrant in way that does not use up all the stack space before it is possible to clean out all pending interrupts. Stack space is the big question here.

Priority levels are normally processed only when more than one interrupt is pending at the same time.

Some processors have special interrupts that can not be disabled(non maskable interrupt), and will always be executed. This is a special superhigh priority interrupt, and used sparingly, even if available. I've seen it used only one time, and that was an emergency interrupt with higher priority than power fail. I suppose exactly power fail could be such a high priority source, in any system.

Gorgon said:

Note that you have to reeable the interrupt system in the ISR yourself.

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Gorgon, in the PIC family the interrupts for the current priority are automatically turned off as the ISR is enetered and re-enabled by the return ('retfie') instuction that terminates the ISR. If you enable it within the ISR it would likely cause problems.

Brian.

betwixt said:

Gorgon, in the PIC family the interrupts for the current priority are automatically turned off as the ISR is enetered and re-enabled by the return ('retfie') instuction that terminates the ISR. If you enable it within the ISR it would likely cause problems.

Brian.

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Yes, I suppose that is the general idea of my post too? Most processors I've used from different brands will disable the interrupt when entering the ISR, and you need to control interrupt enable yourself to get a reentrant interrupt system. That is generally a very bad idea in itself , for any processor family.