gmish27
Member level 1
hello there! Can someone please tell me in a verilog project the simulation carried after synthesis is done on the basis of the hardware made or on the basis of the sequence of codes written in the .v file???
and if i wrote various assign statements sequentially in my project then during simulation is the execution being carried out line-by-line or only synthesis is done line-by-line???
and if i wrote various assign statements sequentially in my project then during simulation is the execution being carried out line-by-line or only synthesis is done line-by-line???