Re: What happen when connect the N-well and P-sub to the gro
If the N-well contains transistors, by tying the N-well to ground you will have lutch-up issues. Remember that between drain and body of P-Mos you have a diode with the N-side being the N-well.
Re: What happen when connect the N-well and P-sub to the gro
Hi,
In the layout, the N-well is of a varcap, if we tying the N-well and P-sub to ground by contact, the ERC reports warning, how to connect can avoid this issue?
Re: What happen when connect the N-well and P-sub to the gro
U will definetly get the latchup issue. during DRC verification u will get theMulti stap error( ie Wells at different potentials).The N-Well and the P-substrate junction forms a diode which should be always be reverse biased to avoid the minority carrier injuction to the substrate which causes the triggering of thr parasitic BJT wht we used to call this phenemonon as the Lath up.So to avoid this we have to connect the N-Well to the VDD.Same for the case of the P-sub also.
Re: What happen when connect the N-well and P-sub to the gro
vijay.kumarreddy said:
U will definetly get the latchup issue. during DRC verification u will get theMulti stap error( ie Wells at different potentials).The N-Well and the P-substrate junction forms a diode which should be always be reverse biased to avoid the minority carrier injuction to the substrate which causes the triggering of thr parasitic BJT wht we used to call this phenemonon as the Lath up.So to avoid this we have to connect the N-Well to the VDD.Same for the case of the P-sub also.
In the varcap, the P+ area inside Nwell is connected with the N-well. So at least two junctions (P+/Nwell and Nwell/Psub) of the PNPN structure are zero biased. I don't think latchup is an issue in this situation.