the spurs in PLL , can also come from the reference which called reference spurs ,
it come from the periodic behoavior of switching in the PFD when the PLL is locked
1. Reference spur is because of the incomplete canceling of the positive and negative charpepump current puses. In locked condition there is typical minimum on time for both.
2. Fractional spurs happen because of the nonlinearity of the transfer function phase difference to charge. So high frequency shaped sigma-delta noise gets folded into the low frequency range where there is no filtering like for the reference noise.
There are many papers describing the effect but the best is to model for your own and derive circuit specification. You will be surprised that high quality analog really matters.
If you look for fractional spurs set the sigma-delta synthsizer to a frequency with an offset frequency equal of the PLL bandwidth to a integer division ratio.
So for a reference frequency of 10MHz and a synthesizer frequency of 2.5GHz and a PLL bandwidth of 100kHz the next avaible small fraction is
(250+1/128)*10MHz=2.5GHz+10MHz/128
The difference frequency of 78.125kHz will not be filtered by the PLL loop filter. The sigma-delta promise high-frequency shaping which is based on complete low frequency canceling. If that not happen because og nonlinearity you get spurs at multiples of 78.125kHz!
Excuse for the question! Why you have so many posts but only 2 helps?
if the control signal of the vco varies periodically, u will see frequency spur in ur vco output.
u can easily analyze that as ppl analyze FM signal spectrum.
Spurs can also appeared by the reason of PFD's dead zone.
If the phase error is too small, the PFD can not detect it, then the control line of VCO will not constant, and the spurs are formed.