ruwan2
Member level 5
- Joined
- Nov 29, 2011
- Messages
- 90
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,286
- Activity points
- 2,141
Hi,
I learn verilog-AMS with an evaluation software SMASH. Its example project has .cir file extension.
Especially could you explain the blue line meaning to me?
I see one of its child file has .va extension, whose content shows it is a verilog-ams file.
thanks,
....................
.lib IdealDiode.va
.ELABORATE work.diode_ckt
.Trace Tran IN(diode_ckt.G[b2].POTENTIAL) V(DIODE_CKT.T2) Min=-1.0000000e+00 Max=3.0000000e+00
.Trace Tran V(DIODE_CKT.T2) Min=-1.0000000e+00 Max=3.0000000e+00
.Trace Tran V(DIODE_CKT.T2) Min=-1.0000000e+00 Max=3.0000000e+00
.Trace Tran V(DIODE_CKT.T1) Min=-1.0000000e+00 Max=3.0000000e+00
.H 1fs 1fs 10ns 125m 2
.Tran 10ns 20us 0s noise=no noisestep=1us
.Method TRAP sync=lockstep
.PivMin 1e-030
.Temp 27
.Step TEMPER 0 1 LIN 100m
I learn verilog-AMS with an evaluation software SMASH. Its example project has .cir file extension.
Especially could you explain the blue line meaning to me?
I see one of its child file has .va extension, whose content shows it is a verilog-ams file.
thanks,
....................
.lib IdealDiode.va
.ELABORATE work.diode_ckt
.Trace Tran IN(diode_ckt.G[b2].POTENTIAL) V(DIODE_CKT.T2) Min=-1.0000000e+00 Max=3.0000000e+00
.Trace Tran V(DIODE_CKT.T2) Min=-1.0000000e+00 Max=3.0000000e+00
.Trace Tran V(DIODE_CKT.T2) Min=-1.0000000e+00 Max=3.0000000e+00
.Trace Tran V(DIODE_CKT.T1) Min=-1.0000000e+00 Max=3.0000000e+00
.H 1fs 1fs 10ns 125m 2
.Tran 10ns 20us 0s noise=no noisestep=1us
.Method TRAP sync=lockstep
.PivMin 1e-030
.Temp 27
.Step TEMPER 0 1 LIN 100m