I am curious about What factors affect to propagation delay from gate to gate?
Uh...the parasitic capacitance, the gates themselves due to process variations, temperature, voltage (that PVT stuff).
u24c02 said:
I'm not too sure, but I think this is mean register to register.
Uh, you have gate to gate above, using the terminology "gate" usually means things like buffers, and, or, nor, nand, xor, xnor, inverter, etc gates, not Flip-Flops.
u24c02 said:
I'm not too sure, ... But not sure.
If you are a student, then I really think you need to go back and retake some of your classes as there are holes in your knowledge.
If you are already out of school, then you need to go back and retake some classes
at a different school to correct those holes in your knowledge.
The vast majority of the numerous questions you've been posting are things which you should know if you graduated. I might be alone in this, but I don't regard edaboard as a substitute for a credentialed university education in engineering, but purely as a resource to get some help on thorny problems you may be having and have no local "mentor" to help you out (which certainly includes all of the hobbyists).