What factors affect the Pd value in SNDR calculation?

[lhlbluesky]

SNDR=signal to noise and distortion ratio
ENOB=(SNDR-1.76)/6.02

in calculation, SNDR=10log(Ps/(Pn+Pd)), Ps is signal power, Pn is noise power, Pd is distortion power, i want to know, what factors effect Pd? in my opinion, Pd is caused by circuit nonlinearity, such as nonlinear on resistance of switch, finite DC gain of opamp, etc.

am i right? if not, please correct me. what is the reason of larger Pd? and how to decrease Pd in circuit design (for good enob)?

please help me, thanks all.

 

[A_Galaxy]

Re: about SNDR

Its been a while but here goes nothing: lets pick an ADC (ex: SAR ADC) there is a comparator (lots transistors in there), S/T Switch, Capacitors in the DAC, Switches associated with the capacitors. Lets say you are designing 100MHz 6Bit ADC, right.
So where does distortion come from: if you send a sine wave you should get some steps on the other side resembling a somewhat sine wave.

source 1: the sampling and track switch almost always introduces some distortion, either because of the variable ON resistance, charge sharing, clock-feedthrough, etc you can look-it up. if you want to know more about switches let me.
Source 2: mismatches in comparators: mostly mismatches in the differential inputs of the comparator; they can be either Vth or Width or Length mismatches which introduce DNL or INL (distortion)
so if you can find your designs DNLs or INLs then you can calculate your total distortion too.
Source 3: bottom plate parasitics associated with Capacitors. for example: you put 10Pf cap and then 20Pf cap, but there is technology mismatch associated with the design. can vary from 1% to more depending on what Sigm is your design is for. basically, parasicts introduce distortion
Source 4: your clock is too fast and the voltages on some nodes are not settling close enough to their final value; which is a source of distortion again.

Well, i may not be clear on all the topics, but i wrote the stuff on top of my head. they are all correct, but may not be coherent enough.
good luck

 

[lhlbluesky]

about SNDR

thanks A_Galaxy, can you say more clearly about:
1, what is the relationship of switch and distortion? how to decrease the distortion by switch?
2, what is the relationship of DNL\INL and distortion?
3, why can parasitics introduce distortion?
4, why can incomplete settling introduce distortion?
please explain to me, thanks,

 

[lhlbluesky]

about SNDR

any ideas?

 

[steadymind]

Re: about SNDR

I cannot say how to reduce the distortion without know the full circuit, but the way i debug is to verilog/verilogA/verilogAMS models .

I start with an ideal one lets say for the switch then, add a some nonlinearity to it ie. make ur switch resistance a function of input voltage, see if the difference in distortion power. this usually is a good way to see how much each block in your design contributes to your performance

what adc specs are you targeting?