[SOLVED] what does this error mean??"Illegal sequential statement"

[fahim1]

hi
i have the following code,that i use component inside it.but have the same errors and warnings for each line of component,i dont understand the errors.

---

Code VHDL - [expand]
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library ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;    --package needed for signed
--use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
-----------------------------------------
entity firserial is
--generic  (n :integer :=4;   --number of coefficients 
          --m :integer :=4);   --number of bits represent coefficients
port( x : in std_logic_vector (3 downto 0);
      clk,rst : in std_logic;
      y : out std_logic_vector (7 downto 0));       
end firserial;
------------------------------------
architecture firserial_arch of firserial is
--------------------------------------
component serialnew2 is
port(a,b : in std_logic_vector(3 downto 0);   
  clk : in std_logic;
  out3 : out std_logic_vector(7 downto 0));
end component;
---------------------------------------
type registers is array (2 downto 0) of std_logic_vector(3 downto 0);
type coefficients is array (3 downto 0) of std_logic_vector(3 downto 0);
signal reg : registers := ("0000","0000","0000");
constant coef : coefficients := ("0001","0010","0011","0100");
-----------------------------------
 
--------------------------------
begin
process(clk,rst)
variable acc,prod : std_logic_vector (7 downto 0) := (others => '0');
variable a,b,c : std_logic_vector(7 downto 0) := (others => '0') ;
begin
-----------------reset--------------------
if rst='1' then 
   for i in 2 downto 0 loop
       for j in 3 downto 0 loop
             reg(i)(j) <= '0';
         end loop;
   end loop;
-------------register inference + MAC -----------
elsif (clk'event and clk='1')  then
acc :=  (others => '0');
--acc := coef(0)*x ;  ok 
--prod := coef(1)*reg(2)+coef(2)*reg(1)+coef(3)*reg(0);
u1 : serialnew2 port map (coef(0), x,clk , acc);
u2 : serialnew2 port map (coef(1), reg(2),clk , a);
u3 : serialnew2 port map (coef(2), reg(1), clk, b);
u4 : serialnew2 port map (coef(3), reg(0), clk, c); 
prod := a+ b+ c ;
acc := acc + prod ;
reg <= x & reg(2 downto 1 );
end if;
y <= acc;
end process;
end firserial_arch;

---

 

[sharath666]

U cannot instantiate a component within a process block. It should be done outside the process block. Also check where you are mapping out3 port of the component to.

 

[fahim1]

U cannot instantiate a component within a process block. It should be done outside the process block. Also check where you are mapping out3 port of the component to.

thanks for answering
i have to do this line inside a process and sequential ,do u have any idea what can i do instead??

 

[TrickyDicky]

From the look of the code, and your reply - you do not understand HDL coding.
Components are not like a function in C - they are like a chip on a circuit board. So calling them inside a process is like trying to make a circuit board that constantly adds and removes chips while the board is running - physically impossible.

You need to instantiate the components outside the process and connect them via signals.

 

[fahim1]

From the look of the code, and your reply - you do not understand HDL coding.
Components are not like a function in C - they are like a chip on a circuit board. So calling them inside a process is like trying to make a circuit board that constantly adds and removes chips while the board is running - physically impossible.

You need to instantiate the components outside the process and connect them via signals.

thanks for answering,
every time i ask a question u keep saying i dont understand hdl coding,but i think i should mention that i am a beginner and i am trying to learn it.
and every time a person ask a question it means that someone have problem in this part and it doesnt necessery means that he or she knows nothing,
again thanks for answering and helping
regards

 

[Dan Mills]

Fahim, you seem to be coming at HDL from the perspective of a programmer, this DOES NOT WORK, you need to start by drawing circuit diagrams then translating those into HDL, if you cannot draw a circuit for whatever you need the thing to do, you likely canot convert it to HDL....

Draw the circuit of what you want (and, or, nand, nor, xor, simple arithmetic + flipflops), and at least initially make all the flipflops D types clocked from a common clock, then translate that diagram into HDL.

Don't view a HDL as a programming language, view it as a description of a circuit.

Regards, Dan.

 

[fahim1]

Fahim, you seem to be coming at HDL from the perspective of a programmer, this DOES NOT WORK, you need to start by drawing circuit diagrams then translating those into HDL, if you cannot draw a circuit for whatever you need the thing to do, you likely canot convert it to HDL....

Draw the circuit of what you want (and, or, nand, nor, xor, simple arithmetic + flipflops), and at least initially make all the flipflops D types clocked from a common clock, then translate that diagram into HDL.

Don't view a HDL as a programming language, view it as a description of a circuit.

Regards, Dan.

thanks Dan,I will try .

 

[sharath666]

As I told you, do it outside a process block. Read a HDL book or browse relevant content on the web to learn it the right way.

 

[ads-ee]

Fahim, you seem to be coming at HDL from the perspective of a programmer, this DOES NOT WORK, you need to start by drawing circuit diagrams then translating those into HDL, if you cannot draw a circuit for whatever you need the thing to do, you likely canot convert it to HDL....

Draw the circuit of what you want (and, or, nand, nor, xor, simple arithmetic + flipflops), and at least initially make all the flipflops D types clocked from a common clock, then translate that diagram into HDL.

Don't view a HDL as a programming language, view it as a description of a circuit.

Regards, Dan.

Fahim, how many times do forum members have to keep saying this same thing? I've stated this multiple times to your posts, but every time you come back with another question where you are obviously still approaching VHDL as a programming language, showing us code that wasn't converted from a circuit diagram of the function.

Fahim, if you really want to learn how to code in VHDL, then do what you've been requested to do by multiple members...draw a circuit diagram of the logic first.
If you have problems with code you've written from that circuit (schematic) then post both the circuit and the code, so we can point out the translation problems or perhaps the errors in your design.

 

[fahim1]

Fahim, how many times do forum members have to keep saying this same thing? I've stated this multiple times to your posts, but every time you come back with another question where you are obviously still approaching VHDL as a programming language, showing us code that wasn't converted from a circuit diagram of the function.

Fahim, if you really want to learn how to code in VHDL, then do what you've been requested to do by multiple members...draw a circuit diagram of the logic first.
If you have problems with code you've written from that circuit (schematic) then post both the circuit and the code, so we can point out the translation problems or perhaps the errors in your design.

i know u said it before and i thank u,but this code is totally different.i wrote it just for simulation for a homework.
yes i remember u said to me before that i should write codes according to schematic,i wanted to learn it for my own but the codes that i posted before was just for simulation thats because i didnt do what u say,i will do that for my next codes,thanks

 

[ads-ee]

If the code is purely for testbenching and driving a UUT (which was designed as a circuit) then using a software approach works to some extent, but the usage of a instantiated component is still bounded by the fact that instantiated components are like putting IC chips on a board.

 

[wtr]

You might need to stop the use of component signal out3 in the expression

prod := a+ b+ c ;

You need to use a temporary signal.
a_int or whatever.

Because you are using the component instantiation inside a process (BAD) ...the compiler is freaking out at the use of an output signal in a expression.

You need to utilize VHDL's concurrent ability more.