The lower the -X the faster the FPGA. The speed is specified in terms of the tpd (pin-to-pin delay) parameter in the FPGA datasheet. This affects the maximum operating frequency of your design in that particular FPGA.
For cpld, the lower the faster. It represent the delay of pin-to-pin.
For Xilinx fpga, the bigger the faster.
It does not represent the delay of pin-to-pin.
The sign is actually punctuation called a "hyphen", which some of us also call a "dash". On the Xilinx FPGA, the speed grade is printed on the chip on a separate line, without the hyphen.
According to my experience description of speed grade vary with company of FPGA producer.Altera is quite different from Xilinx.
more smaller more faster( device 4 is faster than 5)