What does <signal name>.BLIF does not fanout error mea

[bjaminn]

Fanout Problems

I am somewhat new to VHDL and PLDs. I recently wrote some bidirectional code using INOUT. When I synthesize in Lattice ispLEVER i get a warning that says <signal name>.BLIF does not fanout. What is fanout and what does this error mean?

 

[papyaki]

Re: Fanout Problems

Hi,

Fanout is related to an output. Fanout is the ability for an output of a given technology to drive inputs of the same technology connected to this output.

In opposition, an input has a parameter named Fanin.

Fanout and Fanin values dont have any unit. They are expressed by a simple numerical value.

For example, if an output has a Fanout of 10, then the sum of the Fanin of all the inputs connected to this output must not exceed 10.

If the sum of the Fanin is higher than the Fanout, the logical levels of the output are not guarented.

If this is the case, you can use buffers to distribute a logical signal. Clocks inside an fpga are distributed to all the macrocells by this way.

 

[bjaminn]

Re: Fanout Problems

Thank you but I still don't understand how that can be fixed. Is my code too complicated?

 

[papyaki]

Re: Fanout Problems

Hi,

I have never used ispLEVER, but check if an output drives your signal.

Regards.

 

[ashishjindal76]

Fanout Problems

best way is to use the inout buffer which is a bidirectional buffer. this is how u can elliminate ur error.

ashish

 

[r_e_m_y]

Re: Fanout Problems

hi,

It is preferable not to use internal INOUT signals. If you can dissociate input signal from output signal, it is easier for the synthesiser to compile your design.

A other way to solve your problem is to check the number of flip-flop connected on your signal. If this number is too important, the synthesiser can not associate your vhdl to a hardware RTL description corresponding to the device you've selected. You can generate two identical signals and add the preserve_signal attribute (I don't know the correct name of if this attibute for ISP) to this signal in the vhdl code : the synthesiser will not simplify the design. Then, separate the flipflop connected to this signal in two groups : the fan out will be devided by two.

Hope this will help you :wink: