What does pad limited in I/O library mean?

[ee484]

What is pad-limited? I see this term in my I/O library. A pad in my IO library is said to be pad limited.

What does this mean?

I also see core-limited. What does this core-limited or pad-limited refer to?

Best,
B

 

[gevy]

minimum die size for given number of io pad

There are two versions of I/O Cells - PAD-limited and Core-Limited.
PAD-Limited I/O Cells permit to place maximum numbers of PADs.
Core-Limited I/O Cells make minimum area of chip layout if core is small enough.
PAD-Limited I/O Cells are differ from Core-Limited I/O Cells by layout.

 

[cmos_dude]

die size pad limited

Core Limited design is where the size of the core is relatively high when compared to the number of I/O cells, thus leaving ample space for the I/O cells and sometimes even free space after their placements. This results in the die size being decided as a function of the core size.

In the case of a pad-limited design, the core size is small, but the I/O count is proportionally high and hence the size of the die is limited by the number Pads and not the core.
In order to reduce the die size to a minimum, the arrangement of the I/O's is in a staggered fashion where the bond pads are placed in a staggered way thus enabling more number of I/O's in the same die size.
Whereas in the Core limited design, having ample space for I/O's enables the desiners to place them in an inline fashion.

The things will be much clearer looking at the pics attached.