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Fan-out of 4 is a concept in electronics referring to the gate capacitance between two consecutive stages. In recent CMOS processes, it is generally the case that the minimum delay in an inverter chain occurs when each succeeding inverter has a gate capacitance 4 times larger than that of the previous inverter. Since an inverter is the simplest CMOS logic element, using units of FO4 rather than time is a way of referring to delay in a process-independent way.
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