Re: check
the general ASIC design flow:
RTL ---> synthesis---->add test logic(DFT, MEMBIST,etc)--->PR--->tapout
the conformal check is used to check function equivalence of code between two phase. The RTL code is always gold.
I.E. after we do DFT or other, the funciton of netlist may be different from RTL code. So, we need to check whether the function of netlist after PR is equal to function of RTL.
The detailed info, pls refer to LEC tool's manual.
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