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Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed. Most transistor-transistor logic (TTL) gates can feed up to 10 other digital gates or devices. Thus, a typical TTL gate has a fan-out of 10.
In some digital systems, it is necessary for a single TTL logic gate to drive more than 10 other gates or devices. When this is the case, a device called a buffer can be used between the TTL gate and the multiple devices it must drive. A buffer of this type has a fan-out of 25 to 30. A logical inverter (also called a NOT gate) can serve this function in most digital circuits.
Fanin of a cell is all the other cells that drive the cell.
Fanout of a cell is all the other cells driven by the cell.
Take a look at following link to see how GOF trace the fanin/out on a schematic.
Below you can find example on how to calculate fan-out ..
All currents (in mA) are given for standard TTL gates, for different gates these currents can be found in gates' data sheets ..
It looks like current is the parameter that determines fan-out. How about delay? Initially, I thought that delay time is the parameter that cost fan-out.
I have a doubt.As per the example given,you said sourcing current .5 is the max. OK I accept it.Because if the device loaded than .5 each component will get less current so that they might not turn ON.
But why the sinking current has to be less than 20. Can you throw some light on to it.
There is no such a requirement that the sinking current in this example must be <20mA ..
It is (n * 2mA) which has to be smaller or equal to 20mA .. and from this equation one can estimate the number 'n' ..
That's all ..
How to calculate the input current and output current? Is it governed by the equa
I(sat) = k/2 • W/L • (Vgs - Vt)² and I(lin) = k/2 • W/L • [2(Vgs-Vt)Vds-Vds²]?
As far as I know, CMOS inverter does not consume any current in steady-state. So does it mean that the current you mention above is the current yield during switching? Or it is avg current?
gud question weng...actually the explaination above explains drive strength concept for a BJT where inout current i.e base current is essential for the switch to work....now in a MOS this scenario is totally changed....here it is important to charge and discharge load capacitances rather than supply base currents hence the concept of delay also appears as pointed by someone earlier.... now what we actually do is to calibrate a standard gate load an then as per fanout requirement with those loads we apply a input to given design with varible slew's...u cna find this data in delay matrix of any standard cell library...this is how cells are characterised...
hope im of some help...
the number of fanout is that the caculate number the output drive of a gate is connect to the other cell input load. The input load is define in the library.
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