What do 'If-Else' statements synthesize to?

I know that the switch case statements synthesize to Multiplexers.

What do 'If-Else' or 'If-ElseIf' statements synthesize to?

Thank you.

it is really depends what you are trying to impliment. also keep in mind when you are implimeting state mashine you are using case statement, but it is not implimentig as MUX. You can use Simplfy to see RTL model of your design

Regards,

when you code for a combinational circuits........... if-else statments mostly synthesize to mux

But Iouri siad it really depends on what you are trying to implement.............

I am trying to comprehend a VHDL code.

I believe it is a sequential circuit as the code consists of nested if-else statements in a 'process' as follows:-

//
process (list-of-parameters)
begin

if (condition) then
statements

elseif (condition) then
if (condition) then
statements
else (condition) then
statements

elseif (condition) then
.
.
.

and so on......

end if;
end process;
//

What would the synthesized structure look like?

Pardon my ignorance but I'm new to this.

Thnak you.

I am not sure why do you need this. Because, ferstiveal inside FPGA it will come down LUT, ALUT, LE depends what famaly/vendor you are using
Second, all vendor have coding style guideline, where you picking up statement according to the logical function you are trying to impliment
Thirdly syntezis tools like Simplify or Leonardo offers you ability to see how you code implimets.
For example if take regular MUX we can use to discribe:
1. IF then, elsif statements
2. Selective signal assigment out <= in1 when else in2 when ....
3. Case statement
As you can see I pointed there are ways of implimeting MUX (might be more I not an expert), but bottom line is it will take exact the same amount of recourses and will do exact the same function. But coding style is totally different


Good luck!!! Regards,


Iouri

In VHDL, if-then-else produces a piority encoder. The case statement
produces a simple mux.

Gunship

a priority encoder

if-elseif with a clock event synthesizes to a register, or circuits with register components. (For example, shift registers and counters.)

if-elseif without a clock event and missing assignments for some cases - synthesizes to a latch.

if-elseif without a clock event and an assignment for every case - reduces to Boolean logic.

The following code (where f is defined in every case)
reduces to

It is up to your code.
Most of combination circuit should be priority multiplexer.
But for DFF, maybe enable of DFF or reset or etc.

Theoratically all the above discussions are correct. But as I said "theoratically"...
If you are using a decent sysnthesis tool, it will optimise the logic in a very good way. So you may see some part of the logic implemented as mux and some may be as preority encoder.
The tool basically goes through the nested if tatements and generatlly tries to put the circuit to optimise timing. In this process, it uses all the combinations of MUX and encoder or even simple gates to ensure that the logic has minimum delay.
hence if you see the end design spitted out of synthesis tool; be ready for a shock!!

sarath51 said:

a priority encoder

Click to expand...

That's it, agree with you.