What do 1.5 bit and 2.8 bit per stage mean for pipelined ADC?

[A.Anand Srinivasan]

in pipelined ADC the 1.5bit per stage and 2.8bit per stage etc are frequently used and i know the actual procedure and the functions of the stages.... can someone tel me the reason behind the naming and the other such namings that are in use....

 

[hr_rezaee]

1.5 bit, 2.8 bit

HI
because of DEC (digital error correction).
you must first study basic of pipeline adc.
see some theses.
regards

 

[safwatonline]

1.5 bit, 2.8 bit

i think N=log2(# of comparators)

 

[sangueda2007]

Re: 1.5 bit, 2.8 bit

Hi,

I am currently working on pipeline ADC and as per my knowlage there
is no any architecture which is of 2.8Bits/stage instead it is 2.5 Bits/Stage...
Please correct me if I am wrong.
1.5Bits/Stage and 2.5Bits/Stage indicates that you have a room for comparator
offset and also for other nonlinearities,which does not effect the linearity and overall
required bits.
But we can get only 1 and 2 effective number of bits from the respective 1.5bits and
2.5 bits/stage which addes to latency.

Hope this helps you, Please give your feedback on this.

Thanks,
Sangamesh

 

[PaloAlto]

1.5 bit, 2.8 bit

BTW. Does DEC correct also the hysteresis of the comparators in every stage?

 

[rfsystem]

Re: 1.5 bit, 2.8 bit

The story ist very simple:

if the number of comparators for each residual stage is

7

the effective number of bits is

log(7)/log(2)=2.8bits/residual stage

but typical you use only 2 bits, so the lower integer number, and the remaining headroom for correction purposes

The imperfection typical corrected is gain and offset. The imperfection representation are typical the input related levels of the comparator.