What different IC5.0 nd IC50_33

[mitchell]

oasis simulation interface cadence pricing

Dear All:
Does anyone know waht's different with IC5.0 and IC50.33 ? Does it
include the Assure tools ? Thanks

 

[tlihu]

32760 cadence hspice

Products included in Release- IC50
Product # Product Name Version
111 Cadence(R) Design Framework II 5.0
11701 Dracula(R) 2-Level Hierarchical Basic Bundle Dracula 4.8
11702 Dracula(R) 2-Level Hierarchical Advanced Bundle Dracula 4.8
11703 Dracula(R) 2-Level Hierarchical Bundle with RC Extraction Dracula 4.8
11710 Dracula(R) Distributed Second CPU Option Dracula 4.8
12141 Cadence(R) Design Framework Integrator's Toolkit 5.0
14000 Preview Front-End Floorplanner System 5.0
14010 Preview Basic Floorplanner System 5.0
14020 Virtuoso(R) Preview 5.0
14040 Preview Timing Budgeter 5.0
20240 DecChip 21064 Verilog-XL(R) Model DECchip 1.3
206 Virtuoso(R) Simulation Environment 5.0
21060 Virtuoso(R) Schematic VHDL Interface 5.0
21400 Virtuoso(R) Schematic Editor Verilog(R) Interface 5.0
26400 Veritime Timing Analyzer 1.5
276 Virtuoso(R) Schematic Editor HSPICE Interface 5.0
300 Virtuoso(R) Layout Editor 5.0
3000 Virtuoso(R)-XL Layout Editor 5.0
302 Virtuoso(R) Schematic Layout Option 5.0
305 Virtuoso(R) Compactor 5.0
312 Diva(R) Interactive Design Rule Checker 5.0
314 Diva(R) Interactive Electrical Rule Checker 5.0
316 Diva(R) Interactive Layout Parameter Extractor 5.0
318 Diva(R) Interactive Parasitic Resistance Extractor 5.0
32100 Virtuoso(R) Analog Oasis Run-Time Option 5.0
32120 Virtuoso(R) Electronic Design for Manufacturability Option 5.0
32150 Cadence(R) SPICE 5.0
322 Diva(R) Interactive Layout Vs. Schematic Verifier 5.0
32500 Virtuoso(R) Spectre(R) Circuit Simulator 5.0
32501 Virtuoso(R) Spectre Model Interface Option 5.0
32505 Spectre(R) Third-party Simulator Interface 5.0
32510 Spectre(R) Verilog-A Simulation Option 5.0
32520 Virtuoso(R) Spectre(R)-RF Simulation Option 5.0
32521 Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF+G199 5.0
32760 Virtuoso(R) Analog HSPICE Interface Option 5.0
34500 Virtuoso(R) Schematic Editor 5.0
34510 Virtuoso(R) Analog Design Environment 5.0
365 Dracula(R) Graphical User Interface 5.0
370 Virtuoso(R) Layout Synthesizer 5.0
37100 Switched Capacitor Layout Generators 5.0
501 ModuleMaker 5.0
51100 PIC Designer (Concept) 5.0
550 Structure Compiler 5.0
570 Virtuoso(R) Schematic Composer to design compiler integration 5.0
681 Cadence(R) RC Network Reducer Option 3.0
70000 Virtuoso(R) AMS Designer Environment 5.0
70110 Dracula(R) Design Rule Checker 4.9
70120 Dracula(R) Layout Vs. Schematic Verifier 4.9
70130 Dracula(R) Parasitic Extractor 4.9
70510 Dracula(R) Physical Verification Suite 4.9
70520 Dracula(R) Physical Verification and Extraction Suite 4.9
71110 Diva(R) Design Rule Checker 5.0
71120 Diva(R) Layout Vs. Schematic Verifier 5.0
71130 Diva(R) Parasitic Extractor 5.0
71510 Diva(R) Physical Verification Suite 5.0
71520 Diva(R) Physical Verification and Extraction Suite 5.0
727 Dracula(R) Electrical Rules Checker Dracula 4.8
728 Dracula(R) Layout parameter Extractor Dracula 4.8
729 Dracula(R) Parasitic Resistance Extractor Dracula 4.8
731 Dracula(R) Flat Design Rule Checker Dracula 4.8
733 Dracula(R) Flat Layout Vs. Schematic Verifier Dracula 4.8
761 Dracula(R) 2-level Hierarchical Design Rule Checker Dracula 4.8
763 Dracula(R) 2-Level Hierarchical Layout Vs. Schematic Verifier Dracula 4.8
780 Dracula(R) pattern generation option Dracula 4.9
785 Dracula Access Dracula 4.8
792 Dracula(R) distributed multi-CPU option Dracula 4.8
900 Cadence(R) SKILL Development Environment CAT 97B
940 Virtuoso(R) EDIF 200 Reader 5.0
945 Virtuoso(R) EDIF 200 Writer 5.0
952 Virtuoso(R) EDIF 300 Connectivity Reader/Writer 5.0
953 Virtuoso(R) EDIF 300 Schematic Reader/Writer 5.0
965 APPLICON IN DFW 4.4.1
BTAHVMOS Spectre(R) BTA HVMOS Model Not Applicable
BTASOI Spectre(R) BTA SOI Model Not Applicable
DSMODEL Spectre(R) DALLAS SEMICONDUCTOR Model Not Applicable
NTMODELS Spectre(R) Nortel Models Not Applicable
SCIMODEL SCIMODELS Not Applicable
SPECTREBASIC Spectre(R)-Basic Advanced Circuit Simulator 5.0
STMODEL Spectre(R) ST Models Not Applicable
TW01 Cadence(R) team design manager 5.0
TW02 Cadence(R) team design project adminsitrator 5.0



Products included in Release- IC5033
Product # Product Name Version
111 Cadence(R) Design Framework II 5.0
12141 Cadence(R) Design Framework Integrator's Toolkit 5.0
14000 Preview Front-End Floorplanner System 5.0
14010 Preview Basic Floorplanner System 4.4.2
14020 Virtuoso(R) Preview 4.4.2
14040 Preview Timing Budgeter 5.0
14060 Smartpath 4.4.2
206 Virtuoso(R) Simulation Environment 5.0
207 Waveform 5.0
21060 Virtuoso(R) Schematic VHDL Interface 5.0
21400 Virtuoso(R) Schematic Editor Verilog(R) Interface 5.0
276 Virtuoso(R) Schematic Editor HSPICE Interface 5.0
283 Open Simulation System 5.0
300 Virtuoso(R) Layout Editor 5.0
3000 Virtuoso(R)-XL Layout Editor 5.0
302 Virtuoso(R) Schematic Layout Option 5.0
305 Virtuoso(R) Compactor 5.0
32100 Virtuoso(R) Analog Oasis Run-Time Option 5.0
32101 Cadence(R) OASIS for RFDE 5.0
32120 Virtuoso(R) Electronic Design for Manufacturability Option 5.0
32125 Cadence(R) Analog Corners Analysis Option 5.0
32130 Cadence(R) Analog Circuit Optimizer Option 5.0
32140 Cadence(R) Analog Mixed-Signal Simulation Interface Option 5.0
32150 Cadence(R) SPICE 5.0
32500 Virtuoso(R) Spectre(R) Circuit Simulator 5.0
32501 Virtuoso(R) Spectre Model Interface Option 5.0
32505 Spectre(R) Third-party Simulator Interface 1.0
32510 Spectre(R) Verilog-A Simulation Option 5.0
32520 Virtuoso(R) Spectre(R)-RF Simulation Option 5.0
32521 Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF+G199 5.0
32530 Spectre(R)-RF IC Package Modeler Option 5.0
32760 Virtuoso(R) Analog HSPICE Interface Option 5.0
33015 Virtuoso(R) Core Optimizer 3.0
33016 Virtuoso(R) Core Characterizer 3.0
33301 Cadence(R) Analog Mixed-Signal Back-Annotation Interface Option 5.0
34500 Virtuoso(R) Schematic Editor 5.0
34510 Virtuoso(R) Analog Design Environment 5.0
34511 Spectre(R)-RF Substrate Coupling Analysis Option 5.0
34530 Cadence(R) Analog Distributed Processing Option 5.0
365 Dracula(R) Graphical User Interface 4.9
370 Virtuoso(R) Layout Synthesizer 5.0
37100 Switched Capacitor Layout Generators 5.0
374 Cell Optimization Option for Layout Synthesizer (370) 5.0
501 ModuleMaker 5.0
550 Structure Compiler 5.0
570 Virtuoso(R) Schematic Composer to design compiler integration 5.0
681 Cadence(R) RC Network Reducer Option 3.0
70000 Virtuoso(R) AMS Designer Environment 1.0
70110 Dracula(R) Design Rule Checker 4.8
70120 Dracula(R) Layout Vs. Schematic Verifier 4.8
70130 Dracula(R) Parasitic Extractor 4.8
70510 Dracula(R) Physical Verification Suite 4.8
70520 Dracula(R) Physical Verification and Extraction Suite 4.8
71110 Diva(R) Design Rule Checker 4.4.5
71120 Diva(R) Layout Vs. Schematic Verifier 4.4.5
71130 Diva(R) Parasitic Extractor 4.4.5
71510 Diva(R) Physical Verification Suite 4.4.5
71520 Diva(R) Physical Verification and Extraction Suite 5.0
900 Cadence(R) SKILL Development Environment CAT 97B
90001 Virtuoso(R) Multi-mode Simulation 5.0
940 Virtuoso(R) EDIF 200 Reader 5.0
945 Virtuoso(R) EDIF 200 Writer 5.0
952 Virtuoso(R) EDIF 300 Connectivity Reader/Writer 5.0
953 Virtuoso(R) EDIF 300 Schematic Reader/Writer 5.0
972 SDLIN 5.0
974 CDLIN 5.0
BTAHVMOS Spectre(R) BTA HVMOS Model Not Applicable
BTASOI Spectre(R) BTA SOI Model Not Applicable
DSMODEL Spectre(R) DALLAS SEMICONDUCTOR Model Not Applicable
NTMODELS Spectre(R) Nortel Models Not Applicable
SCIMODEL SCIMODELS Not Applicable
SPECTREBASIC Spectre(R)-Basic Advanced Circuit Simulator 5.0
STMODEL Spectre(R) ST Models Not Applicable
TW01 Cadence(R) team design manager 4.2
TW02 Cadence(R) team design project adminsitrator 4.2