What circuit can make 125MHz clock to 1.25Ghz clock?

[asia]

how to make a clock circuit

What circuit can make 125MHz clock to 1.25Ghz and 1.25GHz clock to 125MHz?
can someone give me some pdfs?
Thanks a lot

 

[amaccormack]

clock 125mhz

You'll want a DLL or PLL to increase the clock speed but going down is much easier: a counter circuit to divide can do that job.

 

[rfmw]

for 125 MHz -> 1.25 GHz one could also filter out the 10th harmonic if 125 MHz is a squarewave.

 

[asia]

Is there any analog methods to realize 1.25Ghz to 125MHz?

 

[sunking]

user a counter for 1.25Ghz to 125MHz

 

[flushrat]

How to use DLL for 125M to 1.25G?
Do you mean generate ten 125M clocks with 0 1/20 2/20 ... 9/20 phase shift,
and let the output clock flip-flop at the rising edge of these clock?

You'll want a DLL or PLL to increase the clock speed but going down is much easier: a counter circuit to divide can do that job.

 

[asia]

I am interesting with the method described by rfmw(for 125 MHz -> 1.25 GHz one could also filter out the 10th harmonic if 125 MHz is a squarewave)
can you give me some pdfs?
Thanks

 

[echo47]

I'm curious too, because a squarewave doesn't have a 10th harmonic.

 

[Borber]

The solution will probably be to use 5th harmonics and then 2nd harmonic, two multipliers in cascade.

 

[rfmw]

Thats right, even harmonics are not present in ideal squarewave, but depending on your signal waveform, there could be even harmonics present. Borber's solution is something worth trying, since one only needs a single multiplier (x2) plus a couple of filters (625, 1250 MHZ).

 

[asia]

I have another question: I think for 1.25Gb/s NRZ signal, the recoveried clock shoudl be 2.5GHz, but
a lot examples are 1.25GHz?why? am I wrong?

 

[electronrancher]

this post is getting way out there! filtering harmonics? your signal is going to be about 40dB down, about as high as the noise floor in a digital chip - i would be surprised if someone could come up with a schematic that actually works. 1.25Ghz? lol!

my vote is for a pll. if you aren't familiar, a pll is a little closed-loop system that drives a VCO to match the input clock, both in frequency and phase. If you want a multiplication, you simply divide the VCO output by 10, now the system drives the VCO until Fout/10 matches the reference frequency, or Fout=10*Fin.

I think you should be searching google for both the basics of the pll, and datasheets of pll's that can generate GHz signals - these are not trivial.