what are translate, map, place and route and a bit stream

i'm somewhat new to fpgas and digital design. i'm using ISE Webpack 11.1 to learn about all of that. after i design something i simply follow a series of steps a tutorial "told" me to do, so that the design could be put onto the fgpa. however i don't know why i'm doing it. out of the steps i take i only understand what synthesis is (this step generates what is called a netlist which consists of gates and flip-flops).

i would really appreciate if someone could explain the meaning of the following terms, what they do and why i need them

translate
map
place and route
bit stream file generation

thanks

Re: what are translate, map, place and route and a bit strea

Translate takes all the netlists and NGC files you generated with Coregen and synthesis and turns it into one big design file.

Mapping takes the the generic logic gates and flipflops described in the design files and turns them into the resources available in the FPGA you've chosen (i.e. slices and IOB's).

The place and route tool decides where in the die the resources will be placed and it will wire them together, to meet the design criteria you have given the tool (timing, area, etc).

The bitfile describes the final configuration and wiring of the FPGA, and downloading it into the FPGA will configure it into the circuitry you have mapped, placed and routed.

r.b.

Re: what are translate, map, place and route and a bit strea

hello cyboman,

rberek has given the process in a nice way.

i would also add the same but in a different context.

suppose you have a logic to be designed . then that logic(ie. gates/ffs etc)
is what you want the fpga to behave like.

for that you write the representation in verilog/vhdl and simulate it.
once simulation is over , you start the final phase of implementing the 'digital logic'
inside the fpga.

'mapping' maps your 'digital logic blocks' to the fpga blocks inside the fpga.
that is, fpga contains very large no of cells and i/o s.
so , 'mapping' maps ur design to 'which cells of fpga correspond to which of ur logic' and also 'io blocks to which input/output signals ' in your design.

place and route comes as next phase. 'routing' , connection takes place here.
fpga contains many long and short lines inside . so , routing simply connects those already available lines to required blocks.

since 'fpga' is a generic device , you are generating a 'bitfile' , which can be understood by fpga. To 'bitfile ' , fpga behave like the design what you wanted .

'bitfile generation ' is akin to your 'microprocesor programming '.(not in strict way).

once you download your ' bitfile' , like microprocessor , your fpga starts behaving like your final design .

( a long reply !)

hope i have answered your query.
cheers,
srizbf
29thapril2010

Re: what are translate, map, place and route and a bit strea

srizbf and rberek

thanks your answers did help.