What are things that make timing closure hard

What are things that make timing closure hard?

Our design will have a specified operating frequency and propagation delays which constitute cell delays and path delays between the cells. The idea of timing closure is to verify that no setup hold violations exist and also figure out what are the false paths in the design which must be ignored in the timing analysis.

To this end, what are common difficulties encountered in timing closure and common mistakes? Any examples would be quite benficial.

As you have already mentioned failure to satisfy the setup and hold times is one of the consequences of not able to close timing..
The main problem in closing timing is the presence of long combinational paths in which the cell delays and the path delays add up to a value greater than the provided constraint..

So the whole problem is that we want to breakdown the critical path to use less stages of logic or else, add a register within this huge combinational block to pipeline it. This way the critical path shall become shorter and the design can work at higher frequency.

That does not sound hard at all. Why then do people end up struggling to close timing? Why is it not piece of cake?

matrixofdynamism said:

add a register within this huge combinational block to pipeline it. That does not sound hard at all. Why then do people end up struggling to close timing? Why is it not piece of cake?

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It's not hard to add registers to a combinational block to pipeline it more. The problem then becomes, how do you fix the design with the added latency so that it functions correctly. In some cases that added latency breaks the design and there is no way to fix it without redesigning the architecture of the block.

That is because when you pipeline you are changing the functionality of the circuit. This may lead to signals getting generated earlier or later. This might impact some other part of the design due to which changes may be required in that part of the design also..

What would go wrong if we instead run the design at a lower frequency so timing is met, rather than try to figure out how to reduce the delay in the critical path?

And by the way, why are hold time violations more rare than setup time violations?

matrixofdynamism said:

What would go wrong if we instead run the design at a lower frequency so timing is met, rather than try to figure out how to reduce the delay in the critical path?

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Your design might then not meet the upper level system requirements for through put or performance.

matrixofdynamism said:

And by the way, why are hold time violations more rare than setup time violations?

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They aren't, they are just easier to correct, see my other post on this.