what are the W/L parameter for PMOS and NMOS

Dear Sir,

I Darshan studying master in VLSI design. In my college Mentor graphic is there, in that i can't find which process technology(nm) is present. So can you help me out to find which process technology present by calculating W/L ratio. W/L= 0.32 um/0.17 um is there.

And can tell me according to different technology 90nm, 65nm, 45nm, 32nm and latest 22nm what are the W/L parameter for PMOS and NMOS respectively..?

Thank You & Regards,
Darshan.

Darshan_Dhameliya said:

... can you help me out to find which process technology present by calculating W/L ratio. W/L= 0.32 um/0.17 um is there.

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You can't tell the process technology size from the W/L ratio of a transistor designed in this process; you just can tell that its process size has to be lower than (or max. equal to) the smaller of both W & L.

Get the actual process size from your instructor, or from the PDK documentation.

Darshan_Dhameliya said:

And can tell me according to different technology 90nm, 65nm, 45nm, 32nm and latest 22nm what are the W/L parameter for PMOS and NMOS respectively..?

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On the other hand you can't tell the W/L ratio of transistors from the process size. In any case. L ≧ process_size. Digital circuits very often use L=min_size_in_this_process_size, analog circuits mostly use a multiple of this L. The W/L ratio itself totally depends on circuit design considerations.

Thank you sir.

Actually sir for my last year project I selected to design " Flash memory ". So sir for design flash memory "Floting gate" is required but I could not find floting gate transistor in PDK for schematic design. After designing schematic I can go for layout.

Sir can I design layout without doing schematic..? what kind of change I can do...? In w/l ratio or other parameter

**broken link removed**

Darshan_Dhameliya said:

... I could not find floting gate transistor in PDK for schematic design.

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You probably won't find any single floating gate transistor in a PDK which offers flash memory. Those memories usually are offered as (sometimes size-configurable) macro blocks with schematic symbols, pre-defined behavioural simulation models, and layout abstracts only, because the foundries usually don't like to publish full layouts of their memory blocks.

Darshan_Dhameliya said:

can I design layout without doing schematic..?

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Sure you can do that - if you know how to - but you wouldn't be able to simulate it without a corresponding simulation model.

Darshan_Dhameliya said:

what kind of change I can do...? In w/l ratio or other parameter

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Try to find a description in a scientific paper. You need to understand the parameters' effect if you want to change them.

Sure you can do that - if you know how to - but you wouldn't be able to simulate it without a corresponding simulation model.

Sir what type of simulation..? I didn't understand..

I know how to design layout but can you teach me what is a necessary step and what is the minimum lembda size to design synchronize layout.

Thank you & Regards
Darshan

erikl said:

Sure you can do that - if you know how to - but you wouldn't be able to simulate it without a corresponding simulation model.

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Darshan_Dhameliya said:

Sir what type of simulation..? I didn't understand..

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Do you just want to paint a picture - i.e. create the layout - and think this is enough? You don't want to know if this transistor would work correctly, as you expect it to work? If you want to know it, you need to simulate this device.

Darshan_Dhameliya said:

I know how to design layout but can you teach me what is a necessary step

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?? what for?

Darshan_Dhameliya said:

... and what is the minimum lembda size to design synchronize layout.

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Depends on your design kit resp. technology.