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Here are some type of sheilding done within mixed signal ICs,
1. Sheilding for clock path (High frequency)
2. Sheilding for data path (High frequency)
3. Sheilding for reference voltages.
4. Sheilding for Bias lines.
Here are some type of sheilding done within mixed signal ICs,
1. Sheilding for clock path (High frequency)
2. Sheilding for data path (High frequency)
3. Sheilding for reference voltages.
4. Sheilding for Bias lines.
Following may help you,
1. If Signal in Met1,
bottom plate --> Poly
top plate --> Met2
Either side --> Contact and Via
Connect all plates to either POWER /GROUND depending on situation.
2. If signal in METx
bottom plate --> Met (x-1)
top plate --> Met(x+1)
Either side --> Via(x-1) and Viax
Connect all plates to either POWER /GROUND depending on situation.
3. For differential signal routing run a GND signal between them.
Following may help you,
1. If Signal in Met1,
bottom plate --> Poly
top plate --> Met2
Either side --> Contact and Via
Connect all plates to either POWER /GROUND depending on situation.
2. If signal in METx
bottom plate --> Met (x-1)
top plate --> Met(x+1)
Either side --> Via(x-1) and Viax
Connect all plates to either POWER /GROUND depending on situation.
3. For differential signal routing run a GND signal between them.
Thankyou dinesh, Can u plz tell me if a signal is to be sheilded, can v provide one side with VDD metal and other side with GND metal sheilding...? if yes why ?
having one side VDD and one side VSS may be problematic if VDD tends to bounce around a bit. this will cause variation. the actual effect can be estimated by calculating the capacitance to the line from the shield and use charge conservation. Also if u have a reference line which is close to supply use VDD and viceversa. this has proved useful . if ur are going to tape out and have lots of clocks , high frequency data i would suggest have a seperate shield bus ( call it SVSS - shield vss) and connect it to VSS at the pad level. this tends to minimise bouncing.
Thankyou dinesh, Can u plz tell me if a signal is to be sheilded, can v provide one side with VDD metal and other side with GND metal sheilding...? if yes why ?
More the shielding more de-coupled cap, and more total cap, more delay, and hence you lose sharper rising and falling edges.
If you use only GND line, and assuming which has finite parasitic resistance and not a separate SVSS line [as mentioned by steadymind] - you add ground bounce. If you use both VDD & GND at an equal distance from signal wire, you may have some advantage of balancing - the VDD-GND difference remains less affected. At the same time your signal is more vulnerable to glitches due to other switching logic [if they are on the same VDD/VSS rail], instead of one attacker you have two now.
Go ahead and check how the rising and falling edges looks in case you shield with VDD instead of VSS, of course I am assuming analysis is post-extraction [i.e. after parasitic extraction].
Check out - if you get any energy advantage [c*vdd^2/2] - in case you use one side with VDD & other with VSS?
If you can drive [have flexibility, Si routing space, design-time, to implement a SVSS feed from PAD methodology, what about using SVSS = VDD+VSS/2?
Analyze the scenario, when the dielectric is loss-less and when lossy.
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