What are the thumb rules for capacitor layout design?

[sowmya]

Capacitor Layout

Hi

For a capacitor layout, it is necessary to have some kind of dummy layer for identification of dielectric. Is there any thumb rule of that sort? I am trying to do an MIM cap. This is the first time I am doing a capacitor layout , more information about capacitor layout would be really helpful.

Sowmya

 

[flyankh]

CAPACITOR LAYOUT

Hi sowmya

Does it need match?

Regards

flyankh

 

[sowmya]

Re: CAPACITOR LAYOUT

Hi sowmya

Does it need match?

Regards

flyankh

Yeah it involves matching.

 

[flyankh]

CAPACITOR LAYOUT

ok,the point is symmetry ,including the device self,the devices between eath other ,the connecting metal,even the dummy...and at the same time ,don't forget the crossing match ways.Use your heart and an artwork will apear in your hand at last.

Regards

flyankh

 

[chinito]

Re: CAPACITOR LAYOUT

looks like you're asking if you should put a layer of some sort between say for example M3 and M4. The answer is no. You don't put any type of dielectric material between cap plates. When things are laid out at the foundry, each metal layer is separated from one another by a dielectric material. hope it clearifies a little.

 

[sowmya]

Re: CAPACITOR LAYOUT

looks like you're asking if you should put a layer of some sort between say for example M3 and M4. The answer is no. You don't put any type of dielectric material between cap plates. When things are laid out at the foundry, each metal layer is separated from one another by a dielectric material. hope it clearifies a little.

Thank U Mr. Chinito. U have cleared my doubt.

Added after 30 minutes:

looks like you're asking if you should put a layer of some sort between say for example M3 and M4. The answer is no. You don't put any type of dielectric material between cap plates. When things are laid out at the foundry, each metal layer is separated from one another by a dielectric material. hope it clearifies a little.

Dear Chinito,

Here is something more i have to say for your responce. U just said there is no need for any layer b/w M3 & M4 as dielctric material is already present b/w metal layers. But this M3 & M4 with dielctric will be running in most of the places in the chip. Then, every place it runs, it should be identifying as caps. So, dont u think there should be some kind of Device identification layer?

regards
Sowmya

 

[Vamsi Mocherla]

Re: CAPACITOR LAYOUT

Definately, there is a device identification layer in every fab for MiM caps. But that layer is not actually processed in a fab. The fab only sees that there is an overlap in two metals. And there is a capacitance formed due to metal wires. That is what we call as parasitics in a wire.

 

[flyankh]

CAPACITOR LAYOUT

Hi,sowmya
At first,I am sorry to misunderstand you questions
In fact,the MiM caps' structure is contains three parts .For example , the M3-M4 caps have the lower plate M3,and the dielectric material is normal process material between M3-M4,BUT the UPPER plate is very special:it is constructed with lots specical VIAs.
These VIAs are not used to connect M3&M4,because they didn't reach the M3 layer, so their bottom and M3 can be used as two plate of a capacitor .The M4 layer just is used to be a wire from upper plate of the cap.

Regards

flyankh

 

[sowmya]

Re: CAPACITOR LAYOUT

Hi,sowmya
At first,I am sorry to misunderstand you questions
In fact,the MiM caps' structure is contains three parts .For example , the M3-M4 caps have the lower plate M3,and the dielectric material is normal process material between M3-M4,BUT the UPPER plate is very special:it is constructed with lots specical VIAs.
These VIAs are not used to connect M3&M4,because they didn't reach the M3 layer, so their bottom and M3 can be used as two plate of a capacitor .The M4 layer just is used to be a wire from upper plate of the cap.

Regards

flyankh

Iam not connecting m3 & m4 by via, it’ll definitely not form a cap at that point. Iam using a separate via for m3 and separate for m4 w.r.t the metals I’ll be using for connection.

Added after 2 minutes:

Definately, there is a device identification layer in every fab for MiM caps. But that layer is not actually processed in a fab. The fab only sees that there is an overlap in two metals. And there is a capacitance formed due to metal wires. That is what we call as parasitics in a wire.

Thanx Vamsi

Added after 2 hours 45 minutes:

Hi,sowmya
At first,I am sorry to misunderstand you questions
In fact,the MiM caps' structure is contains three parts .For example , the M3-M4 caps have the lower plate M3,and the dielectric material is normal process material between M3-M4,BUT the UPPER plate is very special:it is constructed with lots specical VIAs.
These VIAs are not used to connect M3&M4,because they didn't reach the M3 layer, so their bottom and M3 can be used as two plate of a capacitor .The M4 layer just is used to be a wire from upper plate of the cap.

Regards

flyankh

sorry about the previous response, I had completly misunderstood your concept. Now, I get the whole picture what u were trying to say, Now, Tell me what is the benifit we get from that vias which are not reaching M3. How will this capacitor formed b/w vias and m3 help in the overall capacitance??

Regards
sowmya

 

[sunny153]

Re: Capacitor Layout

For MiM cap, most of the fabs will supply CTM layer i.e. Capacitor top metal layer.