Then you should be more SPECIFIC by asking for Timing Violation because when you said Timing, it is a very broad topic.
When it comes to Setup and Hold time violation and requirement, you should be concerned about your VLSI, if not ASIC design, by checking Static Timing Analysis thoroughly.
And you better make sure your test vectors have all these verified.
Pin placement has nothing to do with setup and hold time. It is the logic (if any glitches or race conditions), critical path, domain clock (jitter if any, depending your clock layout) that you implement in your VLSI (or ASIC) that determine if you violate setup and hold.
In CPLD, you can only improve your algorithmic design (behavioural or structural) to improve setup and hold time. You cannot control anything else.