What are the pros and cons of having a dedicated S/H stage?

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hyy95120

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I found that in many pipeline ADC designs, a S/H stage is included (vin-->S/H-->stage 1-->stage 2...), however, in other designs, S/H was included in the 1st stage. (vin-->stage1-->stage2...)

What are the pros and cons about having a dedicated S/H stage?


Thanks!
 

S/H in pipeline ADC

I am sorry, can you give some example / paper ..
which depicts this thing ?
 

S/H in pipeline ADC

Without front_end S/H block, that would contribute to aperture errors.
There are S/H capacitors in stage1, but it can't guarantee the sub-ADC's sample same as MDAC's sample.
in other word: Vin must go to two blocks in every stage, if without front_end S/H block, the Vin is variable.

Added after 7 minutes:

It will be save power and die size if absence of front_end S/H block. You can modify the timing in stage1 to reduce the aperture errors as without FE S/H block.
You can reference IEEE paper:
"A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC" by Iuri Mehr and Larry Singer March 2000 Solid-state Circuits IEEE.
 

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    hyy95120

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S/H in pipeline ADC

thank you!
Does it mean, if I sacrifice speed and go for a large Cin and longer sampling time, I'll be fine without a S/H block?
 

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