What are the prerequisite to reduce the insertion delay of my block?

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alokkaashyap

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What are the prerequisite to reduce the insertion delay of my block?
Let say i have an upper limit (from top level) of 650ps of insertion delay for my block but currently i am having insertion delay of 900ps.
Now what needs to be done to correct the insertion delay?
 

Re: How do i reduce the insertion delay of my block?

You need to trace the longest path and check whether it is reasonable or not?
Few examples which cause huge insertion delay, if you have tighter skew limit inorder to meet the skew requirement tool might add more buffers causing huge insertion delay.
If the clock gaters are not cloned properly or not placed properly which might lead to detours.
Usage of low drive buffers 1X or 2X buffers etc.. etc..
 
Re: How do i reduce the insertion delay of my block?

There are a couple ways you can evaluate the problem and fix.
Look over the logic trees and try to reduce the depth of them. Do things in parallel where ever possible. Even if you duplicate some logic, it may help meet your timing.
If you can affort it, add a pipeline (register) delay mid point in the logic. This assumes the logic is clocked.
 

Re: How do i reduce the insertion delay of my block?

Sckoran,He is concerned about the clock insertion delay not the datapath delay ..
 

Re: How do i reduce the insertion delay of my block?

Its is a tradeoff between insertiona delay and skew of clock tree synthesis step
 

Re: How do i reduce the insertion delay of my block?

Hi dftrtl,

Please explain how the skew minimization between flops can increase overall insertion delay ?? I mean if skew is reduced between flops by putting more buffers then how the sum total of these cumulkative skews ( max insertion delay ) will increase ?

Regards,
Nitin
 

Re: How do i reduce the insertion delay of my block?


Hey I didn't quite understand what you meant. Can you please elaborate or point me to an website that does ? thanks.
 

Re: How do i reduce the insertion delay of my block?

first the initial question never indicate clock or data but overall delay of a block.
So now, alokkaashyap, could you indicate which delay you want to reduce?
if it is on a combinational data path delay, you need to look at the cell used for that, and check if the architecture need to be change to reduce mux tree or othr stuff...
if it is a clock delay, you need to add constraints for that particular module.
 

Re: How do i reduce the insertion delay of my block?


Cumulative skew is not insertion delay. Insertion delay is the time taken for clock to reach the CK pin of the flop from its source. By adding buffers to the path with least buffers in a launch-capture pair of flops, the difference in the latency/insertion delay for capture and launch (i.e the skew) is reduced. This increases the latency for the flop in whose clock path the buffers were added.
 
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Re: How do i reduce the insertion delay of my block?


Hi,

Skew of clock signal makes some contribution for the next flip-flop's insertion delay.... Because it also considers when the delay between source path and the Clk pin of 2nd Flip-flop is considered..

Am i right?... correct me if i am wrong..

And i want to know is there anyway we reduce this delay in the synthesis tool itself...

Thanks...

- - - Updated - - -


Hi,

In the measures we take to reduce the skew between pins, we need to match the clock paths by using any logic combination it may be buffers, inverters or transmission gates... So we are introducing some delay because of the "Matching Logic" we used...

This may be the reason for the increased delay we are getting..

Thanks....
 

Re: How do i reduce the insertion delay of my block?


Hey, the difference in insertion delay is skew. If you add the skew to the insertion delay for a launch flop, you get the insertion delay for the responding capture flop. Simple math.
 
Re: How do i reduce the insertion delay of my block?

Thanks Gayathri.
 

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