What are the post GDS activity performed in FAB?

[Raptor]

POST-GDS Activity

HI All,

What are the post GDS activity performed in FAB.Like (OPC ,RET ....).
Can anyone whos got experience in FAB list out the actual steps performed in FAB.

 

[Colbhaidh]

Re: POST-GDS Activity

Post GDS activities :

[1] LVS Layout vs Schematic may be run to check the layout accurately reflects the design.

[2] Add OPC. Optical Proximity correction. This adds to the GDS layout small modifications to take into account diffraction and other effects for the Photolithography and etch processes.
Couple of examples :
A narrow isolated long single line of Poly or say metal may have a different width on the wafer than several dense line together with minimum spacing. The dense lines may print smaller due to diffraction so OPC may increase the widths slightly to compensate.
The narrow line may etch differently than the dense lines, typically the side wall profile may be more sloped. So OPC may add dummy lines next to the isolated line.
Where poly gates run onto isolation, the photo process tends to round the edges which may cause sub threshold leakage close to the isolation edge due to a localised reduction in the width of the poly. So OPC may increase the overlap up over the isolation. A second method is to add hammerheads - make the poly line over isolation look like a T rather than an l.

[3] once OPC is added, the GDS is then run through the Design Rule Checker. This checks for any violations of the Fab's design rule guides - eg two wells too close together, 90 degree poly bends over active etc. etc.
Any such violations are reported to the process owner who will either reject the layout or waive certain design rule violations.

[4] If the layout passes DRC, the GDS is then placed into a frame. This is additional layout around the chip that includes Fab only structures such as individual components that are checked prior to shipping from Fab to make sure transistor etc are within the specified performance limits. Large open boxes at different processing layers the Fab uses to make measurements on individually deposited/grown films, measurement structures for aligning layers to each other for Photolithography, measurement structures for measuring actual physical dimensions, etc.etc.

[5] Once the frame is complete, the field is generated. This is the xy matrix of individual frames that will fit onto the mask for each individual layer. This may be one chip for a Pentium IV (i.e. 1x1) or 100 chips (10x10) for a large logic chip or even 100x100 for an RFID tag chip.

[6] Once the mask layout is complete, the data is then fractured - translated from GDS to MEBES which is used by the mask shop to write the individual masks.

[7] Once the Mebes data is generated (or at the same time) the mask is sized according to Fab requirements. Sometimes when the Fab want a 0.18um feature printed on the wafer, it actually need 0.185um on the reticle. If the reticle is a 4x reduction reticle, then the actual upsize to the mebes data is 4x0.0025um per side
or 0.01um. Note this can be + or - upsize depending on the process.

[8] Once this is done, the mask shop itself may modify the dimensions due its own process offsets. If the contact or via masks use Phase Contrast, then there is further post processing for these masks.

Then its about ready !