I am not an expert on this but answer to your question is: Oversampling converters samples the input signal many times so oversampling and averaging results high resolution at the end. CT SD are used in RF frequencies and oversampling clock needs to be too high in order to oversample enough to get higher resolution. Process dependent clocking speed limits the resolution. Also for RF applications often 6 to 10 bits of resolution is enough.
I think a basic limiting factor there is unideality of components: key, opamp ;noise in MOS, CAP, RES; unideality C(V) character capacitance; you can get more than 20 bit of monotony but not linear.
I think SD adc is not appropriate in low frequency application such as instrument measurement which require very high resolution(18bit more), since the resistor's thermal noise is quite large at low clock frequency. The CT sd ADC's dominant application is in high bandwidth communication and the oversampling ratio is low.Also, the audio can use CT sd ADC.
In SC, you would need a very large Cap to decrease thermal noise ( kT/C ). Likewise, in a continuous-time implementation, you can use a large Cap with smaller resistance to get the same goal.