Hi people,
This is my first post here!
I do simulations to understand behaviour of MOSFET as resistors. I am simulating a very long nmos transistor. My simulation setup is as follows:
W/L=1u/100u
Source is either 0V or 0.3V (To see effect of Vsb)
Drain is varied from 0V up to 3.3V
Gate is either 1.6 or 1.7V.
Tech file is BSIM 0.35um I found it online so I am not sure how correct the process is modelled.
My observations so far are:
1) Length size definitely affects resistance. Longer length higher resistance
2) Gate voltage affects the resistance.
3) Non-zero vsb affects the resistance which all agrees with the theory.
Here is a screenshot of the simulation.
But I have some questions,
1) what really happens when the VSB is non zero.
2)How can we explain the drop behaviour in resistance?
3) What are the ultimate limits of transistor gate length? (I know most of the foundries do not measure very long transistors, but in case we use them how can we model them correctly, what parameters to change?)
4) Least but not least, is there any rules of thumb for maximum length? Like 100 time minimum length ?
Thanks in advance,
I hope this can be an interesting exercise for everybody