What are the effects of these IO constraints?

[designer_ec]

Hi ,please explain each of fallowing topics elaborately.

set_input_delay
set_output_delay
set_drive and set_driving_cell
set_load
Please let me know the what are the effects of each,how these recognize in timing report,how these effect on timing and timing report.

 

[shiv_emf]

set_input_delay explain

hav u refered doc on DC?

 

[energeticdin]

io constraints

The set_input_delay command specifies the amount of
delay from an edge of the CLK clock to the arrival of data on input
pins in1 through in4. It establishes a timing constraint at those
inputs and specifies the arrival time of data with respect to the
CLK clock.
The set_output_delay command specifies the amount of
delay from each output to the external device that captures the
output data. It establishes a timing constraint at the outputs and
specifies the required time for output data with respect to the CLK
clock.

Dinesh

Added after 50 seconds:

set_driving_cell command sets the
driving cell for these ports to the IV (inverter) library cell.

The set_load command sets the external
capacitive load to 1.0 unit for these ports.

Dinesh