Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What are the effects of increasing MOS width on the delay and power consumption?

Status
Not open for further replies.

Yog_571

Newbie level 1
Newbie level 1
Joined
Apr 13, 2013
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,285
I just want to know that what are the effects of increasing transistor width in CMOS on the power consumption and dealy.
 

I just want to know that what are the effects of increasing transistor width in CMOS on the power consumption and dealy.

When you increasing the width of transistors by doing that the parasitic capacitance will also increased thus increased power consumption (because you need more current to charge and discharge the caps...) and delay of the circuit.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top