What the "redundant bits" in multistage ADC or pipeline ADC. Is it intentionally generated or it's error? I am really confused when I am reading the stage optimization on pipeline ADC.
I am going to do a design project on low power pipeline ADC. Could anyone please suggest some good reading materials? I have analog design basic knowledge from graduate classes, but still don't feel very comfortable to understand all the ADC concepts. I need to catch the related concepts quick and start to implement it soon.