What are the edundant bits in multistage or pipeline ADC?

[pekoe]

Q about pipeline ADC

I have a question about pipeline ADC.

What the "redundant bits" in multistage ADC or pipeline ADC. Is it intentionally generated or it's error? I am really confused when I am reading the stage optimization on pipeline ADC.

Thanks a lot !

 

[noiseless]

Re: Q about pipeline ADC

that is for digital correct circuit use later.

 

[pekoe]

Re: Q about pipeline ADC

I see. Thanks a lot!


I am going to do a design project on low power pipeline ADC. Could anyone please suggest some good reading materials? I have analog design basic knowledge from graduate classes, but still don't feel very comfortable to understand all the ADC concepts. I need to catch the related concepts quick and start to implement it soon.

 

[carlyou]

Re: Q about pipeline ADC

This paper may be useful

 

[carlyou]

Re: Q about pipeline ADC

It's good too, it's a PHD thesis of UC berkley.