What are the challenges we should face when we move to 65nm?

[Zeng Jie-jun]

Hi Friends, In 90, we should face the wire delay, SI and IR issues, who can tell me,
from 90nm to 65nm, what are the new chanllenges we should face?
Thanks

 

[nitu]

Re: What are the challenges we should face when we move to 6

Hi..
The issues like wire delay, SI and IR would again be there in 65nm as well.

Leakage is an important issue in 65nm.

I hope it helps..

 

[its_thepip]

Re: What are the challenges we should face when we move to 6

In 65nm , we face probs with these interconnects mainly..and all those which u have mentioned ...
Intel has come out a solution for this probs..It is using Lasers in place of interconnects for its next generation processors ......
Refer the Intel Site for more details...

Added after 5 minutes:

In 65nm , we face probs with these interconnects mainly..and all those which u have mentioned ...
Intel has come out a solution for this probs..It is using Lasers in place of interconnects for its next generation processors ......
Refer the Intel Site for more details...

 

[au_sun]

Re: What are the challenges we should face when we move to 6

challenges in 65nm Tech

 

[rameshsuthapalli]

Hi All,

I am doing the atpg pattern generation and simulations at 65nm.i have to go to the tester lever and i have to debug there.is there any material which wil discribe the problem faced in all these stages.please help me i am new to this technology.

reagdrs,
Ramesh.S

 

[onlymusic16]

Re: What are the challenges we should face when we move to 6

I think leakage arising due to subthreshold currents, is one of the challenges in 65nm. Also the interconnect delay will start posing problems.

 

[master_picengineer]

Hi,
I think electromigration, delays, crostalks and clock skew will be the major problem.

 

[shailendra_gupta]

Hi,

As the technology shrinks the interconnect delays dominate over the gate delay. This is main challenge in lower technology node.
Short channel effect comes into picture. Device will reach into the saturation even before pinch off.
The VIA's resistance get increased as the technology shrinks

 

[yueywcy]

In memory, 65nm means the more Higer k material was used in STORE NODE.