What are modern techniques used in verification of digital systems

I graduated from university only few years ago. I wrote testbench in which I had to manually wiggle each individual signals input signals and then compare the output of the DUT with expected outputs.

Since then I have come to know that there are a lot of very advanced techniques that have been developed to increase efficiency of verification process even if we stay within VHDL/Verilog. The SystemVerilog/SystemC were not covered in my course anyway so I don't know much about them.

I have come across phrases like script based testbench, randomization, assertion based testbench, interfaces e.t.c.

Apparently things have changed a lot over the last 15 years. Is there any source of information that will concisely explain what the different techniques used in verification are nowdays? and which languages are used to implement them?

you can go for uvm or ovm
universal verification methodology
open verification methodology
you can find the details on any website just type these terms on a search engine

these are the latest used for verification