What are chip probe patterns?

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awais980

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Hi,

I am trying to collect information about chip probe patterns, but I could not find much information online.
These patterns are required at tape-out stage. What does these patterns mean? And which tools are used to generate these patterns?
And it seems that these patterns are not part of DFT patterns and they belong to separate category.

Thanks.
 

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Do you mean STIL patterns which are fed to the design for verification before tape-out?
Such patterns can be generated by various ATPG tools, depending on the intented test and the DUT.
 

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dpaul said:
Do you mean STIL patterns which are fed to the design for verification before tape-out?
Such patterns can be generated by various ATPG tools, depending on the intented test and the DUT.
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No. STIL patterns are different and are generated by ATPG tool. CP patterns are different and until now, cannot find much information on this.
 

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