What amount of baud rate error may be acceptable for long time-period on RS232 port?

Status
Not open for further replies.

buenos

Advanced Member level 3
Joined
Oct 24, 2005
Messages
962
Helped
40
Reputation
82
Reaction score
24
Trophy points
1,298
Location
Florida, USA
Activity points
9,143
Hi

What amount of baud rate error may be acceptable for a long time-period on an RS232 serial port?
[%]

In an earlier project, I have used 1% but it has worked rearly. the connection was faulty. after that, I had to replace the microcontroller's (PIC16F877) crystal to a "baud-rate-quarz". then it has worked fine.

Now, I cannot replace the quarz crystal. and I can set the baud rate with a 0.48% error for the required speed. this connection have to be between a TMS320F2811 DSP and a Bluetooth module. Debug is not easy.

Is it depends on the device type?
 

Re: UART baud rate

"Long time" is not really relevant as RS232 is an asynchronous interface - the
reception is synchronised to the start bit.
I know that some MCUs can handle a 3% deviation so you shouldn't have
a problem really.
 

UART baud rate

thanx.
i mean on long time: zero error during an hour.

Added after 28 seconds:

receiving all characters correctly during a time
 

Re: UART baud rate

HI, You can calculate this easy. There are 10 bits in a ASYNC transmission. 8 data bits one stop and one start. The receiver (UART) is re-syncing everytime on the start of a START BIT. so if you want the stop bit to be correctly sampled in the middle of the bit you can see that the maximum error can be: 1/2 BIT in 10 BITS. is 5%. Bo be same stay below 4% + or -

regards,

Paul.
 

Re: UART baud rate

Slight variation can be done in the crystel frequency by changing the value of the capacitor of CLKIN pin 12pf-33pf.
 

UART baud rate

In UART usualy we have 10 bits, 1 start bit 8 data bits and 1 stop bit.
First sampling point from high to low transition of stream is in the Tb/2 (half of baud rate period), and second bit sampling point is 3/2 Tb, ...
suppose 10 bits = 100%
If two system clock rates are different, maximum deviation is half of Tb or 5% (last sampling point).
5% value is marginal, and actually maximum value 2%-3% is tolerable.
but if both side clocks isnt precise, maximum 1%-1.5% can be accepted.

Regards,
Davood.
 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…